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1. 发明授权

US5841445A Image displaying apparatus 失效
标题翻译：图像显示装置
公开(公告)号：US5841445A
公开(公告)日：1998-11-24
申请号：US666595
申请日：1996-06-18
申请人： Toshihiko Hamamatsu , Masayuki Suematsu , Makoto Kondo
发明人： Toshihiko Hamamatsu , Masayuki Suematsu , Makoto Kondo
IPC分类号： H04N5/262 , H04N5/45 , G06F13/00
CPC分类号： H04N5/2624 , H04N5/45
摘要： An image displaying apparatus comprises a line memory from which each line period segment of a first video signal is read during a half line period to produce a first half line period video signal segment, first and second field memories, from each of which each of line period segments contained in each odd or even field period portion of a second video signal is read during a half line period to produce a second or third half line period video signal segment, a signal selector operative to extract alternately the first and second half line period video signal segments to form a first field period video signal portion or extract alternately the first and third half line period video signal segments to form a second field period video signal portion, a dual image display portion for displaying double window picture images in response to the first and second field period video signal portions, an overtaking detector for detecting an overtaking reading condition possibly caused in the first and second field memories, and a writing and reading controller operative to control a timing for writing and reading of the field period portions in the first field memory and a timing for writing and reading of the field period portions in the second field memory so as to suppress defects of display resulting from the overtaking reading and appearing on the double window picture images displayed on the dual image display portion when the overtaking reading condition is detected by the overtaking detector.
摘要翻译：图像显示装置包括行存储器，在半行周期期间从第一视频信号的每个行周期段读取第一半行周期视频信号段，第一和第二场存储器，其中每条行在半行周期期间读取包含在第二视频信号的每个奇数或偶数场周期部分中的周期段，以产生第二或第三半行周期视频信号段，信号选择器可操作地交替地提取第一和第二半行周期视频信号段以形成第一场周期视频信号部分或者交替地提取第一和第三半行周期视频信号段以形成第二场周期视频信号部分，双图像显示部分，用于响应于第二场周期视频信号部分显示双窗口图像图像第一和第二场周期视频信号部分，用于检测可能在冷杉中引起的超车读取条件的超车检测器第一和第二场存储器，以及写入和读取控制器，用于控制第一场存储器中的场周期部分的写入和读取的定时以及第二场存储器中的场周期部分的写入和读取的定时，以便以便在超越检测器检测到超越读取条件时，抑制由于超越读取引起的显示的缺陷，并且出现在双重图像显示部分上显示的双窗口图像图像上。

2. 发明授权

US5537159A Interpolation method and apparatus for improving registration adjustment in a projection television 失效
标题翻译：用于改进投影电视中的配准调整的插值方法和装置
公开(公告)号：US5537159A
公开(公告)日：1996-07-16
申请号：US246131
申请日：1994-05-19
申请人： Masayuki Suematsu , Toshihiko Hamamatsu , Makoto Kondo
发明人： Masayuki Suematsu , Toshihiko Hamamatsu , Makoto Kondo
IPC分类号： H04N5/74 , H04N3/233 , H04N9/28 , H04N9/31
CPC分类号： H04N9/28 , H04N3/2335
摘要： The nonlinear, deflection waveform used improve registration in a three picture tube projection television system is produced using interpolation of stored data setting points by first performing a reduced number of high-order interpolation calculations using the setting points and then performing low-order interpolation calculations either between two calculated high-order interpolated data points or between one of the calculated high-order interpolated data points and one of the setting points. This results in reducing the work load on the central processing unit in the registration system. In addition, a reduced bit-size requirement for the interpolation portion of the registration is obtained by storing registration data of a first bit size and then adding bits below the original LSB for the interpolation calculation prior to performing the digital to analog conversion.
摘要翻译：所使用的非线性偏转波形，通过使用设定点首先进行减数次的高次插值计算，然后进行低阶插值计算，通过使用存储的数据设定点的插值来生成三像素投影电视系统的配准，在两个计算的高阶内插数据点之间或者在所计算的高阶内插数据点之一和设定点之一之间。这导致减少注册系统中的中央处理单元的工作负载。此外，通过存储第一位大小的登记数据，然后在执行数模转换之前，将用于内插计算的原始LSB之下的位相加，来获得注册的插值部分的缩小比特大小要求。

3. 发明授权

US4843289A Digital control bus system 失效
标题翻译：数字控制总线系统
公开(公告)号：US4843289A
公开(公告)日：1989-06-27
申请号：US161316
申请日：1988-02-23
申请人： Takao Mogi , Keiji Yuzawa , Yoshinori Komiya , Masayuki Suematsu , Fujio Tagami
发明人： Takao Mogi , Keiji Yuzawa , Yoshinori Komiya , Masayuki Suematsu , Fujio Tagami
IPC分类号： H04B1/20 , H04N5/44
CPC分类号： H04N5/44 , H04B1/205
摘要： Digitally controllable ICs or function blocks in an electronic apparatus are connected through control bus lines, and a switch device is provided for disconnecting one of the digitally controllable ICs or function blocks from the control bus so that the control bus is not disabled when that one IC is turned off or is not occupied when the IC is operating in its internal processing mode. Therefore, communication between the remaining ICs can be maintained through the control bus.
摘要翻译：电子设备中的数字可控IC或功能块通过控制总线连接，并且提供开关装置用于将数字可控IC或功能块中的一个与控制总线断开，使得当该一个IC 当IC处于其内部处理模式时，它被关闭或不被占用。因此，可以通过控制总线来保持剩余IC之间的通信。

4. 发明授权

US08116594B2 Image processing apparatus, image processing method, and program 有权
标题翻译：图像处理装置，图像处理方法和程序
公开(公告)号：US08116594B2
公开(公告)日：2012-02-14
申请号：US12082625
申请日：2008-04-10
申请人： Masayuki Suematsu , Takayuki Ohe , Masato Usuki , Masanari Yamamoto , Kenkichi Kobayashi
发明人： Masayuki Suematsu , Takayuki Ohe , Masato Usuki , Masanari Yamamoto , Kenkichi Kobayashi
IPC分类号： G06K9/32
CPC分类号： H04N19/577 , H04N19/132 , H04N19/587 , H04N19/87
摘要： An image processing apparatus includes: a detecting unit configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining unit configured to determine whether the input image signal in terms of a level meets a predetermined condition; and an interpolating unit configured such that if the input image signal is not found to meet the predetermined condition, then the interpolating unit interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the input image signal and a preceding input image signal that precedes the input image signal, in accordance with the motion vector, and if the input image signal is found to meet the predetermined condition, then the interpolating unit allows the input image signal to be output unchanged as the input image signal intermediate signal.
摘要翻译：一种图像处理装置，包括：检测单元，被配置为从作为每个时间顺序输入像素的图像信号的输入图像信号中检测运动矢量; 确定单元，被配置为确定所述输入图像信号是否满足预定条件; 以及内插单元，被配置为使得如果没有发现输入图像信号满足预定条件，则内插单元插入并输出在输入图像信号和前一输入之间的预定时间点插入的输入图像信号中间信号根据运动矢量在输入图像信号之前的图像信号，并且如果发现输入图像信号满足预定条件，则内插单元允许输入图像信号作为输入图像信号中间信号而不变地输出。

5. 发明申请

US20090059074A1 Display apparatus 审中-公开
标题翻译：显示装置
公开(公告)号：US20090059074A1
公开(公告)日：2009-03-05
申请号：US12229374
申请日：2008-08-22
申请人： Masayuki Suematsu , Takayuki Ohe , Masato Usuki , Masanari Yamamoto , Kenkichi Kobayashi
发明人： Masayuki Suematsu , Takayuki Ohe , Masato Usuki , Masanari Yamamoto , Kenkichi Kobayashi
IPC分类号： H04N5/50
CPC分类号： H04N5/44504 , H04N7/014 , H04N21/431 , H04N21/44008 , H04N21/440281
摘要： A display apparatus including an image processing unit for performing a frame rate conversion process of converting a frame rate using an interpolating image generated based on a motion vector between adjacent frames with respect to a picture signal which is a collection of image signals of a plurality of frame units taken along a time-series; and a display unit for displaying a picture based on the picture signal of after the frame rate conversion process; wherein the image processing unit performs the frame rate conversion process using an image at least one part of which is the same as a frame immediately before as the interpolating image when an OSD superimposed picture signal having an OSD image signal superimposed on an input picture signal is input to the frame rate conversion section.
摘要翻译：一种显示装置，包括：图像处理单元，用于执行使用基于相邻帧之间的运动矢量生成的内插图像来转换帧率的帧速率转换处理，所述图像信号是多个图像信号的集合的图像信号沿时间序列拍摄的帧单位; 以及显示单元，用于基于帧速率转换处理之后的图像信号显示图像; 其中，当具有叠加在输入图像信号上的OSD图像信号的OSD叠加图像信号是图像处理单元时，使用其至少一部分与紧邻的帧相同的图像作为内插图像执行帧速率转换处理输入到帧速率转换部分。

6. 发明申请

US20080253691A1 Image processing apparatus, image processing method, and program 有权
标题翻译：图像处理装置，图像处理方法和程序
公开(公告)号：US20080253691A1
公开(公告)日：2008-10-16
申请号：US12082619
申请日：2008-04-10
申请人： Masayuki Suematsu , Takayuki Ohe , Masato Usuki , Masanari Yamamoto , Makoto Haitani
发明人： Masayuki Suematsu , Takayuki Ohe , Masato Usuki , Masanari Yamamoto , Makoto Haitani
IPC分类号： G06K9/54
CPC分类号： H04N5/775 , H04N5/445 , H04N5/50 , H04N5/781 , H04N5/85 , H04N7/014 , H04N21/44008 , H04N21/440281
摘要： In the present invention, there is provided an image processing apparatus including: a detecting section configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining section configured to determine whether the input image signal is cleared; and an interpolating section configured such that if the input image signal is not found cleared, then the interpolating section interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the uncleared input image signal and a preceding input image signal that precedes the uncleared input signal, in accordance with the motion vector; and if the input image signal is found cleared, then the interpolating section allows the input image signal to be output unchanged as the input image signal intermediate signal.
摘要翻译：在本发明中，提供了一种图像处理装置，包括：检测部，被配置为从作为每个时间顺序输入像素的图像信号的输入图像信号中检测运动矢量; 确定部，被配置为确定所述输入图像信号是否被清除; 以及被配置为使得如果未找到输入图像信号被清除的内插部分，则内插部分插入并输出在未清零的输入图像信号和先前输入图像信号之间的预定时间点插入的输入图像信号中间信号，在未被清除的输入信号之前，根据运动矢量; 并且如果输出图像信号被清除，则内插部分允许将输入图像信号作为输入图像信号中间信号不变地输出。

7. 发明授权

US5389975A Video additive information identifying device with plural inputs 失效
标题翻译：具有多个输入的视频附加信息识别装置
公开(公告)号：US5389975A
公开(公告)日：1995-02-14
申请号：US048508
申请日：1993-04-20
申请人： Yasuhito Maeshima , Masayuki Suematsu , Masahiro Nakano
发明人： Yasuhito Maeshima , Masayuki Suematsu , Masahiro Nakano
IPC分类号： H04N5/44 , H04N7/01 , H04N7/015 , H04N7/08 , H04N7/081 , H04N7/088 , H04N9/77 , H04N5/46 , H04N5/445 , H04N7/087
CPC分类号： H04N7/0122 , H04N7/088
摘要： In a video additive information identifying device, one of plural video signal inputs each containing a video ID signal is inserted as video additive information on one line at a predetermined position within a vertical blanking period. The selected video signal input is subjected to a Y/C separation processing, and the video ID signal of the selected video signal is extracted from a Y-signal after separation to identify the content of the extracted video ID signal, that is, a frame mode. On the basis of the identification result, a display frame mode of a video display is controlled to be corrected.
摘要翻译：在视频附加信息识别装置中，将包含视频ID信号的多个视频信号输入之一作为视频添加信息插入到垂直消隐期间的预定位置的一行上。对所选择的视频信号输入进行Y / C分离处理，并且从分离后的Y信号中提取所选择的视频信号的视频ID信号，以识别所提取的视频ID信号的内容，即帧模式。基于识别结果，控制视频显示的显示帧模式以进行校正。

8. 发明授权

US4858006A Method and apparatus for establishing a servicing mode of an electronic apparatus 失效
标题翻译：用于建立电子设备的维修模式的方法和装置
公开(公告)号：US4858006A
公开(公告)日：1989-08-15
申请号：US203165
申请日：1988-06-07
申请人： Masakazu Suzuki , Masayuki Suematsu , Yoshinori Komiya
发明人： Masakazu Suzuki , Masayuki Suematsu , Yoshinori Komiya
IPC分类号： H03J1/00 , H03J9/06 , H04N5/44 , H04N5/63 , H04N17/00
CPC分类号： H03J1/0033 , H04N5/44 , H03J9/06
摘要： In controlling an electronic apparatus, such as, a color television receiver, of the type having signal processing circuits which are individually adjustable in accordance with respective control signals provided by a microcomputer or central processing unit (CPU) in response to data corresponding to predetermined or standardized conditions of the adjustable circuits and which are stored in a non-volatile memory along with a secret code, operating keys selectively actuable to provide input data to the CPU for representing an externally applied code and, in a servicing mode of the receiver, for rewriting the data in the memory and thereby changing the standardized conditions of the adjustable circuits, and inner bus lines connecting the CPU to the adjustable circuits, the non-volatile memory and the operating keys; a standby power supply provides electric power to the CPU at a time when operating keys are actuated for inputting data representing an externally applied code to the CPU, a main power supply is turned on for supplying power to the adjustable circuits and thereby causing the receiver to display a color image, and the servicing mode of the receiver is established only when the externally applied code coincides with the stored secret code and the turning on of the main power supply is effected within a predetermined period after the externally applied code has been made to be coincident with the stored secret code.
摘要翻译：在控制具有根据由微型计算机或中央处理单元（CPU）提供的相应控制信号单独调节的信号处理电路的类型的彩色电视接收机的响应于对应于预定的或可调电路的标准化条件，以及与秘密码一起存储在非易失性存储器中的操作键，以便向CPU提供用于表示外部应用代码的输入数据，并且在接收机的服务模式中为重写存储器中的数据，从而改变可调电路的标准化条件，以及将CPU连接到可调节电路的内部总线，非易失性存储器和操作键; 备用电源在CPU启动操作键时向CPU提供电力，以将表示外部施加的代码的数据输入到CPU，打开主电源以向可调节电路供电，从而使接收器显示彩色图像，并且仅当外部施加的代码与存储的密码一致时才建立接收机的服务模式，并且在外部应用代码已经被制成之后的预定时间段内实现主电源的接通与存储的密码相符。

9. 发明授权

US4751574A Electronic apparatus control system 失效
标题翻译：电子仪器控制系统
公开(公告)号：US4751574A
公开(公告)日：1988-06-14
申请号：US831875
申请日：1986-02-24
申请人： Takao Mogi , Masayuki Suematsu , Kosuke Fujita
发明人： Takao Mogi , Masayuki Suematsu , Kosuke Fujita
IPC分类号： H04L7/08 , H04L12/40 , H04N7/00 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/08 , H04N7/081 , H04N7/04
CPC分类号： H04N5/44
摘要： A control system for an electronic apparatus, such as a television receiver, having a control circuit with a control program in an internal memory sequentially communicates over an internal bus within predetermined intervals, such as within the vertical blanking interval of the television signal, with a plurality of controllable circuits in the television receiver, and the control circuit operates to select and communicate with a specific, selected one of the controllable circuits first, in each predetermined interval, with the remainder of the controllable circuits being subsequently communicated with in the remaining portion of the vertical blanking interval.
摘要翻译：用于具有在内部存储器中具有控制程序的控制电路的诸如电视接收机的电子设备的控制系统通过内部总线按预定间隔（例如在电视信号的垂直消隐间隔内）顺序通信，电视接收机中的多个可控电路，并且控制电路操作以在每个预定间隔中首先选择并与一个特定的所选可控电路进行通信，其余的可控电路随后在其余部分中通信的垂直消隐间隔。

10. 发明授权

US4633313A Method and apparatus for transferring data for digitally controlling video equipment 失效
标题翻译：用于传送数字控制视频设备的数据的方法和装置
公开(公告)号：US4633313A
公开(公告)日：1986-12-30
申请号：US816831
申请日：1986-01-07
申请人： Takao Mogi , Masayuki Suematsu
发明人： Takao Mogi , Masayuki Suematsu
IPC分类号： H04N7/083 , H04B1/20 , H04N5/765 , H04N7/00 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/08 , H04N7/081 , H04N7/084 , H04N7/085 , H04N5/14
CPC分类号： H04B1/20 , H04N5/44 , H04N5/765
摘要： Digital data transfer in a digital television receiver between an internal central processing unit, or an external computer, and the video/audio processing circuitry by way of an internal bus is accomplished efficiently and without producing noise interference by using a high-frequency clock signal and a relatively low-frequency clock signal at different times. The high-frequency signal would normally produce visually perceptable noise, however, it is employed only during vertical blanking intervals, and the low-frequency clock signal, which would not produce visually perceptable noise, is used at all times other than the vertical blanking intervals, whereby noise interference that would be otherwise seen on the visual display of the television receiver is suppressed.
摘要翻译：通过内部总线，在内部中央处理单元或外部计算机与视频/音频处理电路之间的数字电视接收机中进行数字数据传输，并且通过使用高频时钟信号而不产生噪声干扰，在不同时间的相对低频时钟信号。高频信号通常会产生视觉上可听见的噪声，但是仅在垂直消隐间隔期间使用，并且不会产生视觉上可感知噪声的低频时钟信号除了垂直消隐间隔之外的所有时间都被使用从而抑制了在电视接收机的视觉显示器上另外看到的噪声干扰。

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