专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07342826B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07342826B2
公开(公告)日：2008-03-11
申请号：US11713039
申请日：2007-03-02
申请人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
发明人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
IPC分类号： G11C11/34 , G11C5/06
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/30 , G11C2207/005 , G11C2216/22
摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.
摘要翻译：能够进行电气重写的片上非易失性存储器的读取速度增加。非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

2. 发明申请

US20050077943A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050077943A1
公开(公告)日：2005-04-14
申请号：US10958466
申请日：2004-10-06
申请人： Ayako Kakuda , Masamichi Fujito
发明人： Ayako Kakuda , Masamichi Fujito
IPC分类号： G11C16/06 , G11C7/06 , G11C16/02 , H03H11/26 , H03K3/354 , H03K5/00 , H03K5/13
CPC分类号： G11C7/222 , G11C7/04 , G11C7/06 , H03K5/133 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay circuit comprises a constant current source, a delay stage in which an operation delay time of an output relative to an input is determined depending on a constant current produced by the constant current source, and a compensating circuit which compensates for a variation in delay characteristic of the delay stage due to a variation in temperature, a variation in power supply voltage and process variations in the opposite direction. When on resistance and threshold voltage characteristics of the compensating circuit and delay stage vary under the influence of the variations in temperature and power supply voltage or the like, a current (Id) changes following it but a current (Ip) changes so as to cancel it. As a result, the delay stage changes in its delay characteristic such that the influences such as the variations in temperature and power supply voltages are canceled out, and suppresses a variation in delay time. The compensating circuit controls a delay speed by such a current that a current characteristic relative to the variation in power supply voltage or the like becomes opposite to a device characteristic of each MOS transistor of the delay stage.
摘要翻译：延迟电路包括恒流源，延迟级，其中相对于输入的输出的操作延迟时间取决于由恒流源产生的恒定电流，以及补偿电路，其补偿延迟的变化由于温度的变化引起的延迟级的特性，电源电压的变化和相反方向上的工艺变化。当在温度和电源电压等的变化的影响下，补偿电路和延迟级的导通电阻和阈值电压特性变化时，电流（Id）随之变化，但电流（Ip）发生变化从而取消它。结果，延迟阶段改变其延迟特性，使得诸如温度和电源电压的变化的影响被抵消，并且抑制延迟时间的变化。补偿电路通过相对于电源电压等的变化的电流特性与延迟级的各MOS晶体管的器件特性相反的电流来控制延迟速度。

3. 发明授权

US07190615B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07190615B2
公开(公告)日：2007-03-13
申请号：US10810672
申请日：2004-03-29
申请人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
发明人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
IPC分类号： G11C11/34 , G11C5/06
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/30 , G11C2207/005 , G11C2216/22
摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.
摘要翻译：能够进行电气重写的片上非易失性存储器的读取速度增加。非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

4. 发明申请

US20070040595A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20070040595A1
公开(公告)日：2007-02-22
申请号：US11586672
申请日：2006-10-26
申请人： Ayako Kakuda , Masamichi Fujito
发明人： Ayako Kakuda , Masamichi Fujito
IPC分类号： H03H11/26
CPC分类号： G11C7/222 , G11C7/04 , G11C7/06 , H03K5/133 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay circuit includes a constant current source, a delay stage, and a compensating circuit. The delay circuit may compensate for a variation in a delay characteristic of the delay stage due to a variation in temperature, supply voltage and/or process.
摘要翻译：延迟电路包括恒流源，延迟级和补偿电路。延迟电路可以由于温度，电源电压和/或过程的变化而补偿延迟级的延迟特性的变化。

5. 发明申请

US20070153618A1 Semiconductor device 有权
公开(公告)号：US20070153618A1
公开(公告)日：2007-07-05
申请号：US11713039
申请日：2007-03-02
申请人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
发明人： Masamichi Fujito , Yutaka Shinagawa , Kazufumi Suzukawa , Ayako Kakuda , Akira Kato , Toshihiro Tanaka
IPC分类号： G11C8/00
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/30 , G11C2207/005 , G11C2216/22
摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

6. 发明授权

US07148732B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07148732B2
公开(公告)日：2006-12-12
申请号：US10958466
申请日：2004-10-06
申请人： Ayako Kakuda , Masamichi Fujito
发明人： Ayako Kakuda , Masamichi Fujito
IPC分类号： H03H11/26
CPC分类号： G11C7/222 , G11C7/04 , G11C7/06 , H03K5/133 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay circuit includes a constant current source, a delay stage, and a compensating circuit. The delay circuit may compensate for a variation in a delay characteristic of the delay stage due to a variation in temperature, supply voltage and/or process.
摘要翻译：延迟电路包括恒流源，延迟级和补偿电路。延迟电路可以由于温度，电源电压和/或过程的变化而补偿延迟级的延迟特性的变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式