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1. 发明授权

US06934211B2 DRAM with refresh control function 失效
标题翻译： DRAM具有刷新控制功能
公开(公告)号：US06934211B2
公开(公告)日：2005-08-23
申请号：US10602117
申请日：2003-06-23
申请人： Toshikatsu Hazama , Masaaki Kuwagata
发明人： Toshikatsu Hazama , Masaaki Kuwagata
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40622
摘要： A dynamic random access memory (DRAM) has a refresh-control function under control by an internal refresh-control signal. The DRAM includes: a cell array having a plurality of DRAM cells divided into a plurality of blocks, the DRAM cells being driven through word lines for data transfer with bit lines; a decoder to select word lines and bit lines connected to the cell array; a sense amplifier to amplify data on the bit lines; and a refresh controller to limit refresh to the cell array so that at least one externally-accessed block cell among the blocks is refreshed.
摘要翻译：动态随机存取存储器（DRAM）具有由内部刷新控制信号控制的刷新控制功能。 DRAM包括：具有分成多个块的多个DRAM单元的单元阵列，通过字线驱动DRAM单元，用于利用位线进行数据传送; 选择连接到所述单元阵列的字线和位线的解码器; 读出放大器，用于放大位线上的数据; 以及刷新控制器，用于限制对单元阵列的刷新，使得块中的至少一个外部访问的块单元被刷新。

2. 发明申请

US20090115500A1 VOLTAGE GENERATING CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20090115500A1
公开(公告)日：2009-05-07
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

3. 发明授权

US08169253B2 Power circuit including step-up circuit and stabilizing method thereof 有权
标题翻译：电源电路包括升压电路及其稳定方法
公开(公告)号：US08169253B2
公开(公告)日：2012-05-01
申请号：US12608417
申请日：2009-10-29
申请人： Akira Umezawa , Masaaki Kuwagata , Yasuhiko Honda , Gyosho Chin
发明人： Akira Umezawa , Masaaki Kuwagata , Yasuhiko Honda , Gyosho Chin
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , G11C5/145 , H02M2001/0032 , Y02B70/16
摘要： A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.
摘要翻译：电源电路包括参考电位电路，升压电路和转换电路。参考电位电路产生参考电位。升压电路通过增加电源电位来产生所需的内部电位。升压电路包括比较电路，差分放大器电路和开关元件。比较电路输出电位和参考电位之间的比较结果。差分放大器电路由操作控制信号导通或关断。开关元件根据操作控制信号执行开/关控制，并且复位差分放大器电路的输出电位。转换电路将操作控制信号转换成使差分放大器电路的导通周期和开关元件的关闭周期变长。

4. 发明授权

US07750727B2 Voltage generating circuit 失效
标题翻译：电压发生电路
公开(公告)号：US07750727B2
公开(公告)日：2010-07-06
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

5. 发明申请

US20100109627A1 POWER CIRCUIT INCLUDING STEP-UP CIRCUIT AND STABILIZING METHOD THEREOF 有权
标题翻译：包括升压电路的电源电路及其稳定方法
公开(公告)号：US20100109627A1
公开(公告)日：2010-05-06
申请号：US12608417
申请日：2009-10-29
申请人： Akira UMEZAWA , Masaaki KUWAGATA , Yasuhiko HONDA , Gyosho CHIN
发明人： Akira UMEZAWA , Masaaki KUWAGATA , Yasuhiko HONDA , Gyosho CHIN
IPC分类号： G05F1/00
CPC分类号： H02M3/073 , G11C5/145 , H02M2001/0032 , Y02B70/16
摘要： A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.
摘要翻译：电源电路包括参考电位电路，升压电路和转换电路。参考电位电路产生参考电位。升压电路通过增加电源电位来产生所需的内部电位。升压电路包括比较电路，差分放大器电路和开关元件。比较电路输出电位和参考电位之间的比较结果。差分放大器电路由操作控制信号导通或关断。开关元件根据操作控制信号执行开/关控制，并且复位差分放大器电路的输出电位。转换电路将操作控制信号转换成使差分放大器电路的导通周期和开关元件的关闭周期变长。

6. 发明授权

US5544120A Semiconductor integrated circuit including ring oscillator of low current consumption 失效
标题翻译：包括低电流消耗的环形振荡器的半导体集成电路
公开(公告)号：US5544120A
公开(公告)日：1996-08-06
申请号：US224905
申请日：1994-04-07
申请人： Masaaki Kuwagata , Ryosuke Matsuo , Keiji Maruyama , Naokazu Miyawaki , Hisashi Ueno
发明人： Masaaki Kuwagata , Ryosuke Matsuo , Keiji Maruyama , Naokazu Miyawaki , Hisashi Ueno
IPC分类号： G11C11/403 , G11C11/406 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K3/03 , H03K3/354 , H03B5/00
CPC分类号： G11C11/406 , H03K3/0315 , H03K3/354
摘要： A semiconductor integrated circuit includes a bias voltage regulation circuit having variable resistors which are provided between voltage output circuits of higher and lower potential sides and changes corresponding to a specified condition such as V.sub.CC and a temperature. The variable resistors and bias voltage output circuits form a V.sub.CC divider, and the variable resistors properly regulate a bias voltage supplied to an oscillation circuit corresponding to each of the specified conditions. Accordingly, if the oscillation circuit is used in an automatic refresh circuit of a PSRAM, an increase of a refresh operation frequency is suppressed regardless of an increase in V.sub.CC. Since a temperature depending variable resistor causes a resistance value to be reduced by the predetermined characteristics against the temperature increase, it is possible to set an oscillation frequency to provide a desired pause for guarantee of circuit operation. It is possible to provide a ring oscillator having a low dependency of the oscillation frequency on a power source voltage and a temperature characteristic, thereby decreasing its current consumption.
摘要翻译：半导体集成电路包括具有可变电阻器的偏置电压调节电路，其设置在较高和较低电位侧的电压输出电路之间，并且对应于诸如VCC和温度的指定条件的变化。可变电阻器和偏置电压输出电路形成VCC分压器，并且可变电阻器适当地调节提供给对应于每个指定条件的振荡电路的偏置电压。因此，如果在PSRAM的自动刷新电路中使用振荡电路，则与VCC的增加无关地抑制刷新操作频率的增加。由于温度依赖可变电阻器使得电阻值相对于温度升高降低预定特性，因此可以设置振荡频率以提供期望的暂停以保证电路操作。可以提供一种振荡频率对电源电压和温度特性的低依赖性的环形振荡器，从而降低其电流消耗。

7. 发明申请

US20110234284A1 SEMICONDUCTOR BOOST CIRCUIT AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：半导体升压电路及其控制方法
公开(公告)号：US20110234284A1
公开(公告)日：2011-09-29
申请号：US13053778
申请日：2011-03-22
申请人： Masaaki KUWAGATA
发明人： Masaaki KUWAGATA
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H02M2003/075 , H03K2005/00039 , H03K2005/00058 , H03K2005/00202
摘要： According to one embodiment, provided is a semiconductor boost circuit including a pump circuit, a switch signal generating circuit and a clock signal generating circuit. The pump circuit receives a clock signal and performs charge pump operation on the basis of the clock signal to boost an input potential to a set potential. The switch signal generating circuit outputs CLK cycle switch signal when a potential output by the pump circuit reaches a first potential greater than the input potential and less than the set potential. The clock signal generating circuit outputs the clock signal having a first frequency if not receiving the CLK cycle switch signal, and, on the other hand, outputs the clock signal having a second frequency greater than the first frequency if receiving the CLK cycle switch signal.
摘要翻译：根据一个实施例，提供了包括泵电路，开关信号发生电路和时钟信号发生电路的半导体升压电路。泵电路接收时钟信号，并且基于时钟信号执行电荷泵操作，以将输入电位升高到设定电位。当泵电路的电位输出达到大于输入电位并小于设定电位的第一电位时，开关信号发生电路输出CLK周期开关信号。如果不接收到CLK周期切换信号，则时钟信号发生电路输出具有第一频率的时钟信号，另一方面，如果接收到CLK周期切换信号，则输出具有大于第一频率的第二频率的时钟信号。

8. 发明申请

US20100085114A1 HIGH-VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE PROVIDED THEREWITH AND SEMICONDUCTOR INTEGRATED DEVICE 审中-公开
标题翻译：高电压生成电路和半导体存储器件及其半导体集成器件
公开(公告)号：US20100085114A1
公开(公告)日：2010-04-08
申请号：US12564359
申请日：2009-09-22
申请人： Mario SAKO , Masaaki Kuwagata , Gyosho Chin
发明人： Mario SAKO , Masaaki Kuwagata , Gyosho Chin
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C8/08
摘要： A voltage generation circuit includes a pump circuit, a first unit, a first switch, and a first capacitor. The pump circuit generates a first voltage and outputs the first voltage to a first node. The first unit includes a first resistance unit to output a second voltage at a second node. The first switch connects the second node and an output terminal. A resistance value of a parasitic resistance formed in an interconnection from the second node to the output terminal is smaller than a resistance value of the first resistance unit. The first capacitor includes one of electrodes and the other electrodes. The one of electrodes is connected to an interconnection connecting the second node and the first switch element. The other of the electrodes is grounded. A capacitance of the first capacitor element is larger than a capacitance connected to the output terminal.
摘要翻译：电压产生电路包括泵电路，第一单元，第一开关和第一电容器。泵电路产生第一电压并将第一电压输出到第一节点。第一单元包括用于在第二节点处输出第二电压的第一电阻单元。第一个开关连接第二个节点和一个输出端子。在从第二节点到输出端子的互连中形成的寄生电阻的电阻值小于第一电阻单元的电阻值。第一电容器包括一个电极和另一个电极。电极中的一个连接到连接第二节点和第一开关元件的互连。另一个电极接地。第一电容器元件的电容大于连接到输出端子的电容。

9. 发明授权

US5442587A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5442587A
公开(公告)日：1995-08-15
申请号：US68669
申请日：1993-05-28
申请人： Masaaki Kuwagata , Yuji Watanabe
发明人： Masaaki Kuwagata , Yuji Watanabe
IPC分类号： G06F11/20 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/789 , G11C29/842
摘要： In the memory cell provided with spare cells and normal cells, the time required to discriminate the spare column address from the normal column address or vice versa can be reduced, and thereby a high speed memory access can be realized. When an address is given from the counter to a memory circuit having the spare address and the normal address, before the counter outputs an address to the memory circuit, the spare/normal discriminating circuit acquires previously the address outputted from the counter and discriminates whether the address is the spare address or the normal address. On the basis of this discrimination, the select circuits switch the address to be applied from the select circuits to the memory circuit from the normal address to the spare address or vice versa.
摘要翻译：在设置有备用单元和正常单元的存储单元中，可以减少区分备用列地址与正常列地址或反之亦然的时间，从而可以实现高速存储器存取。当从计数器向具有备用地址和通常地址的存储器电路提供地址时，在计数器向存储器电路输出地址之前，备用/正常识别电路预先获取从计数器输出的地址，地址是备用地址或正常地址。基于这种鉴别，选择电路将要从选择电路施加的地址从存储器电路从正常地址切换到备用地址，反之亦然。

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