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1. 发明申请

US20200006115A1 Integrated Circuit with Airgaps to Control Capacitance 审中-公开
公开(公告)号：US20200006115A1
公开(公告)日：2020-01-02
申请号：US16021352
申请日：2018-06-28
申请人： Miriam R. Reshotko , Nafees A. Kabir , Manish Chandhok
发明人： Miriam R. Reshotko , Nafees A. Kabir , Manish Chandhok
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/311
摘要： An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.

2. 发明申请

US20150001724A1 METHOD OF CREATING A MASKLESS AIR GAP IN BACK END INTERCONNECTS WITH DOUBLE SELF-ALIGNED VIAS 有权
标题翻译：在具有双重自对准VIAS的后端互连中创建无障碍空气隙的方法
公开(公告)号：US20150001724A1
公开(公告)日：2015-01-01
申请号：US13931219
申请日：2013-06-28
申请人： Manish CHANDHOK , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
发明人： Manish CHANDHOK , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/32133 , H01L21/32139 , H01L21/76802 , H01L21/7682 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L21/76885 , H01L21/76886 , H01L21/76897 , H01L23/5222 , H01L23/528 , H01L23/53209 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
摘要翻译：一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

3. 发明申请

US20080118849A1 Reflective optical system for a photolithography scanner field projector 审中-公开
标题翻译：用于光刻扫描仪场地投影仪的反射光学系统
公开(公告)号：US20080118849A1
公开(公告)日：2008-05-22
申请号：US11603811
申请日：2006-11-21
申请人： Manish Chandhok , Russell Hudyma
发明人： Manish Chandhok , Russell Hudyma
IPC分类号： G03F1/00 , G03B27/54
CPC分类号： G03F7/70233
摘要： A reflective optical system for a photolithography scanner field projector is described. In one example, the optical projection system has at least eight reflecting surfaces for imaging a reflection of a photolithography mask onto a wafer and the system has a numerical aperture of at least 0.5.
摘要翻译：描述了一种用于光刻扫描仪场地投影仪的反射光学系统。在一个示例中，光学投影系统具有至少八个用于将光刻掩模的反射成像到晶片上的反射表面，并且该系统的数值孔径至少为0.5。

4. 发明申请

US20060093972A1 Active hardmask for lithographic patterning 失效
公开(公告)号：US20060093972A1
公开(公告)日：2006-05-04
申请号：US11293594
申请日：2005-12-02
申请人： Michael Goldstein , Manish Chandhok , Eric Panning , Robert Bristol , Bryan Rice
发明人： Michael Goldstein , Manish Chandhok , Eric Panning , Robert Bristol , Bryan Rice
IPC分类号： G03F7/00
CPC分类号： G03F7/091 , G03F7/11
摘要： In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

5. 发明授权

US07033739B2 Active hardmask for lithographic patterning 失效
公开(公告)号：US07033739B2
公开(公告)日：2006-04-25
申请号：US10423466
申请日：2003-04-24
申请人： Michael Goldstein , Manish Chandhok , Eric Panning , Robert Bristol , Bryan J. Rice
发明人： Michael Goldstein , Manish Chandhok , Eric Panning , Robert Bristol , Bryan J. Rice
IPC分类号： G03F7/20
CPC分类号： G03F7/091 , G03F7/11
摘要： In an implementation, energy reaching the lower surface of a photoresist may be redirected back into the photoresist material. This may be done by, for example, reflecting and/or fluorescing the energy from a hardmask provided on the wafer surface back into the photoresist.

6. 发明授权

US07033734B2 Dipole illumination 失效
标题翻译：偶极子照明
公开(公告)号：US07033734B2
公开(公告)日：2006-04-25
申请号：US10377056
申请日：2003-02-28
申请人： Manish Chandhok
发明人： Manish Chandhok
IPC分类号： G03B27/54
CPC分类号： G03F7/701 , G03F7/70283
摘要： A system for fabricating patterns on a semiconductor, the system includes a first aperture having two openings aligned in a first axis, a first mask, a second aperture having two openings aligned in a second axis, and a second mask. The system may be implemented with the second axis substantially perpendicular to the first axis.
摘要翻译：一种用于在半导体上制造图案的系统，该系统包括具有在第一轴线上对准的两个开口的第一孔，第一掩模，具有在第二轴线上对准的两个开口的第二孔和第二掩模。该系统可以用基本上垂直于第一轴线的第二轴线来实现。

7. 发明申请

US20060072096A1 Lithography alignment 有权
标题翻译：光刻对准
公开(公告)号：US20060072096A1
公开(公告)日：2006-04-06
申请号：US11286367
申请日：2005-11-23
申请人： Manish Chandhok
发明人： Manish Chandhok
IPC分类号： G03B27/54
CPC分类号： G03F9/7076 , G03F7/70283 , G03F9/7015 , G03F9/7049 , H01L21/682
摘要： A wafer may be aligned with an imaging plate including an alignment grating with a pitch P. A pupil filter in the pupil plane of the optical system may be used so that the periodicity of the intensity of light from the alignment grating is less than P at the wafer plane. Thus, an alignment pattern on the wafer having a pitch smaller than the pitch of the alignment grating may be used. For example, the intensity periodicity at the wafer plane may be P/2. In an implementation, a pupil filter may be sized and positioned to block a zero-th order maximum of light transmitted through the alignment grating at the pupil plane. The pupil filter may be sized and positioned to allow first order maxima of the light to pass. The alignment system may be used with transmission or reflection optics.
摘要翻译：晶片可以与包括具有间距P的对准光栅的成像板对准。可以使用光学系统的光瞳平面中的光瞳滤光器，使得来自对准光栅的光强度的周期小于P 晶圆平面。因此，可以使用具有小于对准光栅的间距的间距的晶片上的对准图案。例如，晶片面的强度周期可以是P / 2。在一个实施方案中，瞳孔滤光器的尺寸和位置可以被定位成阻挡在瞳孔平面处透射通过对准光栅的光的零级最大值。瞳孔滤光器的尺寸和位置可以使光的一阶最大值通过。对准系统可以与透射或反射光学元件一起使用。

8. 发明授权

US06982133B2 Damage-resistant coatings for EUV lithography components 失效
标题翻译：用于EUV光刻元件的耐损伤涂层
公开(公告)号：US06982133B2
公开(公告)日：2006-01-03
申请号：US10327599
申请日：2002-12-21
申请人： Manish Chandhok , Kramadhati V. Ravi
发明人： Manish Chandhok , Kramadhati V. Ravi
IPC分类号： G01F9/00
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F1/48 , G21K1/062 , G21K2201/067
摘要： Damage-resistant coatings are provided on radiation-exposed surfaces of EUV lithographic components. The diamond coating provides resistance to particle impingement, cleaning processes, and degradation due to high temperatures. The diamond coating is beneficial when deposited on the reflecting surface of an EUV Si/Mo multilayer mirror, grazing collector incidence mirror, the reflecting surface of an EUV Si/Mo multilayer reflective mask, and radiation-exposed surfaces of EUV debris shield. The diamond coating provides longer lasting EUV components.
摘要翻译：在EUV光刻部件的辐射暴露表面上提供耐损伤涂层。金刚石涂层提供对颗粒冲击，清洁过程和由于高温导致的退化的抵抗力。当沉积在EUV Si / Mo多层反射镜，放电收集器入射镜，EUV Si / Mo多层反射掩模的反射表面和EUV碎片屏蔽的辐射暴露表面时，金刚石涂层是有益的。金刚石涂层提供更持久的EUV组件。

9. 发明授权

US06972843B2 Lithography alignment 失效
标题翻译：光刻对准
公开(公告)号：US06972843B2
公开(公告)日：2005-12-06
申请号：US10648627
申请日：2003-08-25
申请人： Manish Chandhok
发明人： Manish Chandhok
IPC分类号： G03F7/20 , G03F9/00 , H01L21/68 , G01B11/00
CPC分类号： G03F9/7076 , G03F7/70283 , G03F9/7015 , G03F9/7049 , H01L21/682
摘要： A wafer may be aligned with an imaging plate including an alignment grating with a pitch P. A pupil filter in the pupil plane of the optical system may be used so that the periodicity of the intensity of light from the alignment grating is less than P at the wafer plane. Thus, an alignment pattern on the wafer having a pitch smaller than the pitch of the alignment grating may be used. For example, the intensity periodicity at the wafer plane may be P/2. In an implementation, a pupil filter may be sized and positioned to block a zero-th order maximum of light transmitted through the alignment grating at the pupil plane. The pupil filter may be sized and positioned to allow first order maxima of the light to pass. The alignment system may be used with transmission or reflection optics.
摘要翻译：晶片可以与包括具有间距P的对准光栅的成像板对准。可以使用光学系统的光瞳平面中的光瞳滤光器，使得来自对准光栅的光强度的周期小于P 晶圆平面。因此，可以使用具有小于对准光栅的间距的间距的晶片上的对准图案。例如，晶片面的强度周期可以是P / 2。在一个实施方案中，瞳孔滤光器的尺寸和位置可以被定位成阻挡在瞳孔平面处透射通过对准光栅的光的零级最大值。瞳孔滤光器的尺寸和位置可以使光的一阶最大值通过。对准系统可以与透射或反射光学元件一起使用。

10. 发明授权

US06850050B2 Reticle inspection 失效
标题翻译：标线检查
公开(公告)号：US06850050B2
公开(公告)日：2005-02-01
申请号：US10155428
申请日：2002-05-24
申请人： Manish Chandhok , Julian Montoya
发明人： Manish Chandhok , Julian Montoya
IPC分类号： G01R31/305 , G01N27/00
CPC分类号： G01R31/305
摘要： An electric field is induced from a feature of a reticle, and the field is measured.
摘要翻译：从掩模版的特征引起电场，并测量场。

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