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1. 发明授权

US5844924A Main signal memory supervisory control system using odd-even alternative check 失效
标题翻译：主信号存储监控系统采用奇偶校验
公开(公告)号：US5844924A
公开(公告)日：1998-12-01
申请号：US956862
申请日：1997-10-24
申请人： Mamoru Nagamoto
发明人： Mamoru Nagamoto
IPC分类号： G06F11/10 , G11C29/24 , H04J3/14 , H04L1/00 , H04L12/931 , H04Q11/04 , G06F11/00
CPC分类号： G11C29/24 , H04Q11/0478 , H04L2012/5627 , H04L2012/5681
摘要： In a main signal memory supervisory control system which comprises a parity generator, a parity detector, a write address counter and a read address counter, a state management section, a down counter, and a change point detector are arranged as memory supervising means. In this memory supervisory, a state management section receives address generation notifications from the write address counter and the read address counter to calculate and outputs the data accumulation amount of the main signal memory, a down counter subtracts a counter by the read address, sets a predetermined value of a data amount in advance, outputs a change notification when a counter value changes from numerical value "1" to numerical value "0", and loads the predetermined value on the counter, and a change point detector sends an odd-even switching signal of a parity when the change point detector receives the change notification. As a result, an odd-even alternative switching operation for a supervisory parity can be performed even in a memory write system such as an ATM communication system using only effective data, so that supervisory performance for the main signal memory can be improved.
摘要翻译：在包括奇偶校验发生器，奇偶检测器，写地址计数器和读地址计数器，状态管理部分，递减计数器和变化点检测器的主信号存储器监控系统中被布置为存储器监控装置。在这种存储器管理中，状态管理部分从写地址计数器和读地址计数器接收地址生成通知，以计算和输出主信号存储器的数据累积量，递减计数器通过读地址减去计数器，预先设定数据量的预定值，当计数器值从数值“1”变为数值“0”时输出变更通知，并将该预定值加载到计数器上，变化点检测器发送奇偶校验当变化点检测器接收到改变通知时，奇偶校验的切换信号。结果，即使在仅使用有效数据的ATM通信系统等存储器写入系统中也可以执行用于监视奇偶校验的奇偶交替切换操作，从而可以提高主信号存储器的监控性能。

2. 发明授权

US5509005A Power saving time slot interchanger with random read/write cycles 失效
标题翻译：省电时隙交换器，具有随机读/写周期
公开(公告)号：US5509005A
公开(公告)日：1996-04-16
申请号：US315484
申请日：1994-09-30
申请人： Mamoru Nagamoto
发明人： Mamoru Nagamoto
IPC分类号： H04Q11/04 , H04Q11/08 , H04L12/52
CPC分类号： H04Q11/08
摘要： In a switching system of multiple time slot interchangers associated with outlet ports, each interchanger includes multiple data memories respectively connected to inlet ports and connected to the outlet port with which the interchanger is associated. A set of commands is established for each incoming data signal. The command set includes an inlet port number (IPN), an incoming slot number (ISN), an outlet port number (OPN), and an outgoing slot number (OSN). During a write cycle, one of the inlet ports is selected in accordance with the IPN command and one of the data memories which are associated with the selected inlet port is selected in accordance with the OPN command. The selected data memory is caused to store the data signal of an incoming time slot identified by the stored ISN command into one of its storage locations identified by the stored ISN command. During a subsequent read cycle, one of the outlet ports is selected in accordance with the OPN command and one of the data memories which are associated with the selected outlet port is selected in accordance with the stored IPN command. The selected data memory is caused to read a data signal from one of its storage locations identified by the ISN command onto an outgoing time slot identified by the OSN command.
摘要翻译：在与出口相关联的多个时隙交换器的交换系统中，每个交换器包括分别连接到入口端口并连接到与交换器相关联的出口的多个数据存储器。为每个输入数据信号建立一组命令。命令集包括入口端口号（IPN），输入插槽号（ISN），插座端口号（OPN）和输出插槽号（OSN）。在写周期期间，根据IPN命令选择一个入口端口，并且根据OPN命令选择与所选入口端口相关联的一个数据存储器。使选择的数据存储器将由存储的ISN命令识别的进入时隙的数据信号存储到由存储的ISN命令标识的其中一个存储位置。在随后的读取周期期间，根据OPN命令选择一个出口端口，并且根据所存储的IPN命令来选择与所选出口相关联的一个数据存储器。使选择的数据存储器从由ISN命令识别的其中一个存储位置读取到由OSN命令标识的输出时隙上的数据信号。

3. 发明授权

US6163528A Selective cell discard system in ATM switch 失效
标题翻译： ATM交换机中的选择性单元丢弃系统
公开(公告)号：US6163528A
公开(公告)日：2000-12-19
申请号：US188407
申请日：1998-11-10
申请人： Mamoru Nagamoto
发明人： Mamoru Nagamoto
IPC分类号： H04Q3/00 , H04L12/813 , H04L12/823 , H04L12/851 , H04L12/861 , H04L12/927 , H04L12/931 , G01R31/08 , H04L12/28
CPC分类号： H04L49/105 , H04L49/205 , H04L49/30 , H04L49/505 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： Disclosed is a selective cell discard system in an ATM switch to transfer exchanging a cell input from a plurality of input ports to a plurality of output ports, for controlling the selective cell discard to guarantee QOS (quality of service) by controlling the order of cell discard or the read-out order of cells accumulated in cell buffer when a plenty of cells exceeding the exchange capability of the switch is input, the system having: a selective cell discard controller connected to each of the plurality of input ports; a first-stage switch unit comprising all of cell buffers for output port group provided corresponding to output port groups into which the plurality of output ports are divided, and a cell multiplexer which inputs exchanging all of cells to be input from the plurality of input ports through the selective cell discard controller according to routing information of concerned cells; a groups of second-stage switch units which are provided corresponding to each of the cell buffers for output port group and input exchanging a cell in a concerned cell buffer for output port group to any of cell buffers for output port provided corresponding to output ports belonging to a concerned output port group; and means for detecting a congestion in the cell buffer for output port group, and discard-controlling a cell to be input to the concerned cell buffer for output port group in the selective cell discard controller.
摘要翻译：公开了一种ATM交换机中的选择性小区丢弃系统，用于将多个输入端口的小区输入交换到多个输出端口，用于通过控制小区的顺序来控制选择性小区丢弃以保证QOS（服务质量）当输入超过交换机的交换能力的大量单元时，在单元缓冲器中累积的单元的丢弃或读出顺序具有：连接到多个输入端口中的每一个的选择性单元丢弃控制器; 第一级开关单元，包括与输出端口组对应的输出端口组的所有单元缓冲器，所述单元缓冲器对应于所述多个输出端口被分配到的输出端口组;以及单元复用器，其输入从所述多个输入端口交换要输入的所有单元通过选择性细胞丢弃控制器根据相关细胞的路由信息; 一组第二级开关单元，其被提供对应于用于输出端口组的每个单元缓冲器，并且输入将用于输出端口组的相关单元缓冲器中的单元交换到对应于输出端口所属的输出端口提供的输出端口的任何单元缓冲器到有关输出港口集团; 以及用于检测用于输出端口组的小区缓冲器中的拥塞的装置，并且对选择小区丢弃控制器中的输出端口组的相关小区缓冲器进行丢弃控制。

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