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1. 发明授权

US06788135B1 Terminating pathway for a clock signal 失效
标题翻译：终止时钟信号的路径
公开(公告)号：US06788135B1
公开(公告)日：2004-09-07
申请号：US10615549
申请日：2003-07-08
申请人： Lisa Ann Yunker , Eric McCutcheon Rentschler , Peter Shaw Moldauer
发明人： Lisa Ann Yunker , Eric McCutcheon Rentschler , Peter Shaw Moldauer
IPC分类号： H01L2500
CPC分类号： H05K1/0246 , G06F1/10 , G06F1/183 , H01L23/647 , H01L2924/0002 , H01L2924/15311 , H05K1/0243 , H05K2201/10022 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： A signal pathway is presented for routing clock signals from a clock driving device to a circuit component and on to a termination. The signal pathway employs a minimal stub to carry the clock signals to the circuit component without introducing excess signal distortions. A first signal line of the signal pathway is formed on a circuit board and extends from the clock driving device to a first terminal for interfacing with the circuit component. A second signal line of the signal pathway is routed on the circuit component from one end adjacent to and electrically coupled with the first terminal to an opposite end adjacent to and electrically coupled with a second terminal formed on the circuit board. The stub extends from the second signal line on the circuit component. A third signal line of the signal pathway extends on the circuit board from the second terminal to the termination.
摘要翻译：提出了一种信号路径，用于将时钟信号从时钟驱动装置路由到电路部件，并连接到终端。信号通道采用最小短截线将时钟信号传送到电路组件，而不引入过多的信号失真。信号路径的第一信号线形成在电路板上并从时钟驱动装置延伸到用于与电路部件接口的第一端子。信号路径的第二信号线在电路部件上从与第一端子相邻并与其电耦合的一端被引导到与形成在电路板上的第二端子相邻并与其电耦合的相对端。短线从电路元件上的第二条信号线延伸。信号通路的第三信号线在电路板上从第二端子延伸到终端。

2. 发明授权

US07159203B2 Differential delay-line 失效
标题翻译：差分延时线
公开(公告)号：US07159203B2
公开(公告)日：2007-01-02
申请号：US10897745
申请日：2004-07-22
申请人： Lisa Ann Yunker
发明人： Lisa Ann Yunker
IPC分类号： G06F17/50 , G01R31/28 , H01L25/00
CPC分类号： H01P9/00 , H05K1/0245 , H05K1/0248 , H05K1/0286 , H05K3/222 , H05K2201/09263 , H05K2201/10636 , H05K2203/162 , H05K2203/173 , Y02P70/611 , Y10T29/49124
摘要： A printed circuit board is built including metal traces for a differential clock. Within a break in each metal trace pads for a delay line socket are included along with pads for two 0-ohm resistors in series. In between the two 0-ohm resistors metal traces are build in a configuration to provide a specified delay in a signal passing through the trace. This group of pads and traces allows a designer to test (on the completed printed circuit board) differential clocks in modes including negative skew. In normal operation, the 0-ohm resistors are present on the printed circuit board and the clock signals pass through the metal traces build in a configuration to provide a specified delay in the signals passing through the traces. During testing, delay lines may be placed in the delay line sockets and the 0-ohm resistors may be removed. When 0 ns delay lines are placed in the sockets, the clock delays are negatively skewed from normal delay since the clock signals no longer pass through the long metal traces between the 0-ohm resistors.
摘要翻译：构建了印刷电路板，包括用于差分时钟的金属迹线。在延迟线插座的每个金属迹线焊盘的间歇期间，包括串联的两个0欧姆电阻器的焊盘。在两个0欧姆电阻之间，金属迹线建立在配置中，以提供通过迹线的信号的指定延迟。这组焊盘和迹线允许设计人员测试（在完成的印刷电路板上）差分时钟的模式，包括负偏移。在正常操作中，0欧姆电阻存在于印刷电路板上，并且时钟信号通过金属迹线构成一个配置，以提供通过迹线的信号的指定延迟。在测试期间，可以将延迟线放置在延迟线插座中，并且可以去除0欧姆电阻。当插座中插入0 ns延迟线时，时钟延迟与正常延迟负偏差，因为时钟信号不再通过0欧姆电阻之间的长金属走线。

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