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1. 发明授权

US06788135B1 Terminating pathway for a clock signal 失效
标题翻译：终止时钟信号的路径
公开(公告)号：US06788135B1
公开(公告)日：2004-09-07
申请号：US10615549
申请日：2003-07-08
申请人： Lisa Ann Yunker , Eric McCutcheon Rentschler , Peter Shaw Moldauer
发明人： Lisa Ann Yunker , Eric McCutcheon Rentschler , Peter Shaw Moldauer
IPC分类号： H01L2500
CPC分类号： H05K1/0246 , G06F1/10 , G06F1/183 , H01L23/647 , H01L2924/0002 , H01L2924/15311 , H05K1/0243 , H05K2201/10022 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： A signal pathway is presented for routing clock signals from a clock driving device to a circuit component and on to a termination. The signal pathway employs a minimal stub to carry the clock signals to the circuit component without introducing excess signal distortions. A first signal line of the signal pathway is formed on a circuit board and extends from the clock driving device to a first terminal for interfacing with the circuit component. A second signal line of the signal pathway is routed on the circuit component from one end adjacent to and electrically coupled with the first terminal to an opposite end adjacent to and electrically coupled with a second terminal formed on the circuit board. The stub extends from the second signal line on the circuit component. A third signal line of the signal pathway extends on the circuit board from the second terminal to the termination.
摘要翻译：提出了一种信号路径，用于将时钟信号从时钟驱动装置路由到电路部件，并连接到终端。信号通道采用最小短截线将时钟信号传送到电路组件，而不引入过多的信号失真。信号路径的第一信号线形成在电路板上并从时钟驱动装置延伸到用于与电路部件接口的第一端子。信号路径的第二信号线在电路部件上从与第一端子相邻并与其电耦合的一端被引导到与形成在电路板上的第二端子相邻并与其电耦合的相对端。短线从电路元件上的第二条信号线延伸。信号通路的第三信号线在电路板上从第二端子延伸到终端。

2. 发明授权

US07203043B2 Method and structure for external control of ESD protection in electronic circuits 有权
标题翻译：电子电路中ESD保护的外部控制方法和结构
公开(公告)号：US07203043B2
公开(公告)日：2007-04-10
申请号：US10448763
申请日：2003-05-30
申请人： Jason Harold Culler , Peter Shaw Moldauer
发明人： Jason Harold Culler , Peter Shaw Moldauer
IPC分类号： H02H3/20 , H02H3/22 , H02H9/04
CPC分类号： H02H9/046
摘要： A method and structure for external control of an electrostatic discharge (ESD) protection of electronic devices. According to the structure, one or more shunt circuits are coupled to the electronic devices and one or more external contacts are coupled to the one or more shunt circuits. One or more power supplies are further coupled to the one or more shunt circuits prior to the shunt circuits being coupled to the electronic devices. According to the method, the one or more external contacts are operable to be used to perform on or more of: grounding one or more of one or more external contacts coupled to the one or more shunt circuits, supplying one or more DC signals to one or more of the one or more shunt circuits via one or more of the one or more external contacts, and supplying one or more AC signals to one or more of the one or more shunt circuits via one or more of the one or more external contacts.
摘要翻译：一种用于电子设备静电放电（ESD）保护的外部控制的方法和结构。根据该结构，一个或多个分流电路耦合到电子设备，并且一个或多个外部触点耦合到一个或多个分流电路。在分流电路耦合到电子设备之前，一个或多个电源进一步耦合到一个或多个分流电路。根据该方法，一个或多个外部触点可操作以用于执行以下中的一个或多个：将耦合到所述一个或多个分流电路的一个或多个外部触点中的一个或多个接地，将一个或多个DC信号提供给通过所述一个或多个外部触点中的一个或多个的一个或多个分流电路中的一个或多个，并且通过所述一个或多个外部触点中的一个或多个将一个或多个AC信号提供给所述一个或多个分流电路中的一个或多个联系人

3. 发明授权

US06861912B1 Oscillator method and apparatus for a test chip 失效
标题翻译：用于测试芯片的振荡器方法和装置
公开(公告)号：US06861912B1
公开(公告)日：2005-03-01
申请号：US10619909
申请日：2003-07-14
申请人： Jason H. Culler , Peter Shaw Moldauer
发明人： Jason H. Culler , Peter Shaw Moldauer
IPC分类号： H03K3/03 , H03B27/00
CPC分类号： H03K3/0315
摘要： A method and apparatus for modifying a frequency of an oscillating signal comprises generating an oscillating signal of a predetermined frequency on a semiconductor device used as an evaluation test chip by connecting a predetermine number of circuit elements in a ring oscillator configuration. A delay element operably coupled into the ring oscillator configuration modifies the predetermined frequency of the ring oscillator configuration. The operable coupling may occur on a semiconductor package containing the semiconductor device or a circuit board containing the semiconductor device. A ring oscillator is also described.
摘要翻译：用于修改振荡信号的频率的方法和装置包括通过在环形振荡器配置中连接预定数量的电路元件，在用作评估测试芯片的半导体器件上产生预定频率的振荡信号。可操作地耦合到环形振荡器配置中的延迟元件修改环形振荡器配置的预定频率。可操作的耦合可以在包含半导体器件或包含半导体器件的电路板的半导体封装上发生。还描述了环形振荡器。

4. 发明授权

US06922822B2 Verifying proximity of ground vias to signal vias in an integrated circuit 有权
标题翻译：验证接地通孔对集成电路中的过孔进行信号的接近
公开(公告)号：US06922822B2
公开(公告)日：2005-07-26
申请号：US10199668
申请日：2002-07-19
申请人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
发明人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.
摘要翻译：公开了用于在集成电路封装设计中验证接地通孔与信号通路的接近性的技术。包装设计师使用包装设计工具创建包装设计。邻近验证器在包装设计中验证在每个指定信号通道的预定阈值距离内存在接地通孔。邻近验证器可以向包装设计者通知任何不足够接近接地孔的信号通孔，例如通过在显示监视器上显示的包装设计的图形表示中提供这种信号通孔的视觉指示。作为响应，包装设计者可以修改包装模型以确保所有信号通孔足够接近地孔。邻近验证器可以被实现为设计规则，其可以由包装设计工具自动地和实时地执行。

5. 发明授权

US06807657B2 Inter-signal proximity verification in an integrated circuit 失效
标题翻译：集成电路中的信号间接近验证
公开(公告)号：US06807657B2
公开(公告)日：2004-10-19
申请号：US10199331
申请日：2002-07-19
申请人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
发明人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/5081
摘要： In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.
摘要翻译：在一个方面，公开了用于识别和通知集成电路设计中的信号走线的电路设计者比接近阈值更接近的技术。期望信号迹线彼此分开至少接近阈值以将信号间串扰降低到可接受的水平。这种通知可以动态地（电路设计者正在设计电路）或通过在电路设计生成之后产生的报告来进行。在另一方面，公开了用于识别和通知电路设计者最接近参考信号迹线的信号迹线的技术。这种通知可以向电路设计者提供关于电路设计中拥塞的区域的反馈，并且因此可能产生不可接受的串扰水平。

6. 发明授权

US06769102B2 Verifying proximity of ground metal to signal traces in an integrated circuit 有权
公开(公告)号：US06769102B2
公开(公告)日：2004-07-27
申请号：US10199127
申请日：2002-07-19
申请人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
发明人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Techniques are disclosed for verifying the proximity of signal return paths (e.g., ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

7. 发明授权

US07327583B2 Routing power and ground vias in a substrate 失效
标题翻译：在基板中布线电源和接地通孔
公开(公告)号：US07327583B2
公开(公告)日：2008-02-05
申请号：US10939654
申请日：2004-09-13
申请人： Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Karl Bois
发明人： Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Karl Bois
IPC分类号： H01R12/16 , H05K1/11
CPC分类号： H01L23/50 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H01L2924/15311 , H01L2924/3011 , H05K1/0219 , H05K1/0222 , H05K1/0263 , H05K1/0298 , H05K1/112 , H05K1/115 , H05K2201/09627 , H01L2924/00
摘要： A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.
摘要翻译：公开了一种用于在多层衬底中布线过孔的方法。方法的一个实施例可以包括提供具有内部结合表面的多层基底，所述内部结合表面具有多个内部接合垫和具有多个外部键合垫的外部结合表面。基于通孔图案，多个电源通孔和接地通孔可以从内部接合表面和外部接合表面之间的第一再分配层路由到第一再分配层和外部接合表面之间的第二再分配层。通孔图案可以包括以基本上等于与多层基板相关联的最小路由间距的间隔相互隔开相邻的方式布置电力通孔和接地。

8. 发明授权

US07326860B2 Routing vias in a substrate from bypass capacitor pads 失效
标题翻译：从旁路电容器衬垫的衬底中路由通孔
公开(公告)号：US07326860B2
公开(公告)日：2008-02-05
申请号：US11446669
申请日：2006-06-05
申请人： Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Gary Taylor , David Quint
发明人： Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Gary Taylor , David Quint
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/0219 , H05K1/0222 , H05K1/0231 , H05K1/113 , H05K1/115 , H05K2201/09309 , H05K2201/09627 , H05K2201/0979 , H01L2924/00
摘要： A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.
摘要翻译：公开了具有接合面的多层基板。衬底的一个实施例可以包括设置在接合表面上的旁路电容器连接焊盘。旁路电容连接焊盘可能具有旁路电容器功率垫和旁路电容接地垫。衬底还可以包括从旁路电容器功率焊盘路由到与接合表面间隔开的第一再分配层的多个电源通孔和从旁路电容器接地焊盘路由到第一再分配层的多个接地通孔。衬底还可以包括根据功率和接地经由图案阵列从第一再分配层路由到第二再分布层的多个电源和接地通孔，其中多个接地通孔在第一再分配层处被点动到多个电源通孔通过图案阵列形成电源和接地。

9. 发明授权

US07078812B2 Routing differential signal lines in a substrate 失效
公开(公告)号：US07078812B2
公开(公告)日：2006-07-18
申请号：US10929989
申请日：2004-08-30
申请人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
发明人： Mark D. Frank , Jerimy Nelson , Peter Shaw Moldauer
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/544 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L2924/0002 , H01L2924/15331 , H01L2924/3011 , H05K1/0237 , H05K1/0306 , H05K1/112 , H05K1/115 , H05K3/4611 , H05K3/4629 , H05K2201/09236 , H05K2201/09627 , H05K2201/10674 , H01L2924/00
摘要： A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.

10. 发明授权

US07075185B2 Routing vias in a substrate from bypass capacitor pads 失效
标题翻译：从旁路电容器衬垫的衬底中路由通孔
公开(公告)号：US07075185B2
公开(公告)日：2006-07-11
申请号：US10940100
申请日：2004-09-14
申请人： Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Gary Taylor , David Quint
发明人： Jerimy Nelson , Mark D. Frank , Peter Shaw Moldauer , Gary Taylor , David Quint
IPC分类号： H01L23/48
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/0219 , H05K1/0222 , H05K1/0231 , H05K1/113 , H05K1/115 , H05K2201/09309 , H05K2201/09627 , H05K2201/0979 , H01L2924/00
摘要： A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.
摘要翻译：公开了一种用于从旁路电容器焊盘排列多层衬底中的通孔的方法。方法的一个实施例可以包括布置在多层基板的第一表面上与旁路电容器接地垫间隔开的旁路电容器功率垫，将多个电源通孔从旁路电容器功率垫路由到与第二再分布层间隔开的第一再分配层并且将多个接地通孔从旁路电容器接地焊盘路由到第一再分布层。该方法还可以包括将第一再分配层处的多个接地通孔点动到多个电源通孔以提供电源和接地通孔图案，并将电源和接地通孔从第一再分配层路由到间隔开的第二再分配层基于通过图案的功率和接地的第一再分配层。

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