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1. 发明授权

US06429715B1 Deskewing clock signals for off-chip devices 有权
标题翻译：用于片外器件的去抖时钟信号
公开(公告)号：US06429715B1
公开(公告)日：2002-08-06
申请号：US09482741
申请日：2000-01-13
申请人： Shekhar Bapat , Lawrence C. Hung
发明人： Shekhar Bapat , Lawrence C. Hung
IPC分类号： G06F104
CPC分类号： G06F1/10 , H03L7/0814 , H03L7/087
摘要： An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection. This external connection has the same propagation delay as the external connections to the various external devices. Matching of the propagation delays of the various external connections may be accomplished by making the external connections all of the same length.
摘要翻译：集成电路接收外部时钟信号并由此产生提供给多个外部设备的时钟信号。集成电路上的延迟锁定环（DLL），平衡时钟树和多个接口单元一起工作，以将时钟信号提供给多个外部设备，使得每个外部设备的时钟信号进行偏斜校正相对于外部时钟信号。由于不需要平衡时钟树来将集成电路的时钟信号路由到外部设备，因此板级设计被简化，而每个外部设备通过单独的外部连接耦合到相应的一个接口单元。这些外部连接中的每一个具有相等的传播延迟。其中一个接口单元通过外部连接将时钟信号提供给DLL的参考信号输入。该外部连接具有与各种外部设备的外部连接相同的传播延迟。可以通过使外部连接全部相同的长度来实现各种外部连接的传播延迟的匹配。

2. 发明授权

US07725787B1 Testing of a programmable device 有权
标题翻译：可编程器件测试
公开(公告)号：US07725787B1
公开(公告)日：2010-05-25
申请号：US12235489
申请日：2008-09-22
申请人： Robert W. Wells , Shekhar Bapat , Tassanee Payakapan , Shahin Toutounchi
发明人： Robert W. Wells , Shekhar Bapat , Tassanee Payakapan , Shahin Toutounchi
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译：测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。该方法通过向编程的电路提供测试输入来继续。该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。

3. 发明授权

US5920202A Configurable logic element with ability to evaluate five and six input functions 失效
标题翻译：可配置逻辑元件，具有评估五个和六个输入功能的能力
公开(公告)号：US5920202A
公开(公告)日：1999-07-06
申请号：US835088
申请日：1997-04-04
申请人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. The two six-input-function multiplexers or function generators therefore produce two outputs of which one can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions. Some functions of up to nineteen inputs can also be generated in a single CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。根据本发明的CLE具有四个功能发生器。两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。其他两个功能发生器的输出类似地组合。然后，两个五输入功能多路复用器或函数发生器的输出与第六个六输入函数多路复用器或函数发生器中的第六个独立输入组合，并在第六个六输入函数中与不同的第六独立输入进行组合多路复用器或函数发生器。因此，两个六输入功能多路复用器或函数发生器产生两个输出，其中一个可以是六个输入的任何功能; 另外的输出可以是六个输入的任何功能，只要在两个6输入功能之间共享五个输入。也可以在单个CLE中生成多达十九个输入的某些功能。

4. 发明授权

US07310758B1 Circuit for and method of implementing programmable logic devices 有权
标题翻译：电路和实现可编程逻辑器件的方法
公开(公告)号：US07310758B1
公开(公告)日：2007-12-18
申请号：US11208574
申请日：2005-08-22
申请人： Matthieu P. H. Cossoul , Shekhar Bapat
发明人： Matthieu P. H. Cossoul , Shekhar Bapat
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.
摘要翻译：描述了在多芯片模块中采用多个集成电路的方法。该方法包括以下步骤：识别在第一裸片上实现的有缺陷的可编程逻辑器件; 识别在第二管芯上实现的功能可编程逻辑器件; 以及耦合有缺陷的可编程逻辑器件和功能可编程逻辑器件。根据替代实施例，在多芯片模块中采用多个集成电路的方法包括在多芯片模块上配置多个可编程逻辑器件的步骤。还描述了一种多芯片集成电路封装。

5. 发明授权

US6107827A FPGA CLE with two independent carry chains 有权
标题翻译： FPGA CLE具有两个独立的进位链
公开(公告)号：US6107827A
公开(公告)日：2000-08-22
申请号：US311782
申请日：1999-05-13
申请人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called "slices". Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.
摘要翻译：本发明提供了一种包括相同瓦片阵列的FPGA。每个瓦片包括包括可配置逻辑元件（CLE）的逻辑块。在一个实施例中，CLE以称为“切片”的两个相似部分实现。每个切片都有一个单独的进位链。在具有四个功能发生器的CLE中，每个进位链包含两个功能发生器的输出。

6. 发明授权

US5936424A High speed bus with tree structure for selecting bus driver 失效
标题翻译：具有树型结构的高速总线，用于选择公共汽车司机
公开(公告)号：US5936424A
公开(公告)日：1999-08-10
申请号：US950380
申请日：1997-10-14
申请人： Steven P. Young , Kamal Chaudhary , Shekhar Bapat , Sridhar Krishnamurthy , Philip D. Costello
发明人： Steven P. Young , Kamal Chaudhary , Shekhar Bapat , Sridhar Krishnamurthy , Philip D. Costello
IPC分类号： H03K19/0175 , H03K19/173 , H03K19/0185 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/017581
摘要： According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.
摘要翻译：根据本发明，提供一种用于驱动快速且小的总线的结构。代替多个三态缓冲器，每个输入信号一个，多个多路复用器或门连接到树结构中。三态缓冲器的三态使能线路成为控制线，用于使树结构能够将其自己的输入信号放置在总线上，而不是传播已经在总线上的信号。然后，缓冲元件允许从总线中抽出所得到的信号。本发明的一个实施例包括类似于前瞻携带链的前瞻逻辑。这允许大量输入线连接到总线，同时保持高速。树结构的对称延迟使最大延迟最小化，从而增加预测速度。

7. 发明授权

US5847580A High speed bidirectional bus with multiplexers 失效
标题翻译：具有多路复用器的高速双向总线
公开(公告)号：US5847580A
公开(公告)日：1998-12-08
申请号：US729065
申请日：1996-10-10
申请人： Shekhar Bapat , Sridhar Krishnamurthy
发明人： Shekhar Bapat , Sridhar Krishnamurthy
IPC分类号： H03K19/173 , H03K19/0175
CPC分类号： H03K19/1737
摘要： A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output lines of multiple multiplexer chains are combined together using a logic gate chain to create a bus line with a larger number of drivers while substantially maintaining switching speed and flexibility in routability. In one embodiment, two OR chains propagate signals in opposite directions. The top OR chain combines the outputs of all the multiplexer chains to its left. Similarly, the bottom OR chain combines the outputs of all the multiplexer chains to its right. The output of the entire bus is provided at both the leftmost and the rightmost end of the OR chain. The bus output is also provided at tap points by combining the outputs of the top logic gate chain and the bottom logic gate chain using a logic gate. The top logic gate chain provides the outputs of all drivers to the left of the tap point while the bottom logic gate chain provides the outputs of all drivers to the right of the tap point.
摘要翻译：多路复用器链耦合到两个逻辑门，其又在不同方向上传播它们各自的输出信号，由此提供双向信号分配。使用逻辑门链将多个多路复用器链的输出线组合在一起，以创建具有更多数量驱动器的总线，同时基本上保持了可切换的切换速度和灵活性。在一个实施例中，两个OR链沿相反方向传播信号。顶部OR链将所有多路复用器链的输出组合到其左侧。类似地，底部OR链将所有多路复用器链的输出组合到其右侧。整个总线的输出端设在OR链的最左端和最右端。总线输出也通过使用逻辑门组合顶部逻辑门链和底部逻辑门链的输出而在抽头点处提供。顶部逻辑门链提供所有驱动器在分接点左侧的输出，而底部逻辑门链提供所有驱动器在分接点右侧的输出。

8. 发明授权

US07469371B1 Methods of testing a user design in a programmable integrated circuit 有权
标题翻译：在可编程集成电路中测试用户设计的方法
公开(公告)号：US07469371B1
公开(公告)日：2008-12-23
申请号：US11500526
申请日：2006-08-08
申请人： Shekhar Bapat , Mohit Kumar Jain
发明人： Shekhar Bapat , Mohit Kumar Jain
IPC分类号： G01R31/28
CPC分类号： G01R31/318516 , G01R31/318342
摘要： Methods of testing a user design implemented in a programmable integrated circuit (IC). The programmable IC is programmed with a first test design that includes the user design and a first test circuit, and a first test pattern is run. The programmable IC is then programmed with a second test design that includes the user design and a second test circuit, and a second test pattern is run. If one of the test patterns fails and the other passes, the programmable IC passes the test sequence. Because one of the test patterns passed, the error in the other test pattern must have occurred in the test circuit, which is not necessary for the functioning of the user design in the programmable IC. Thus, the success of one test pattern shows that the flawed resource is not included in the portion of the programmable IC utilized for implementing the user design.
摘要翻译：在可编程集成电路（IC）中实现的用户设计的测试方法。可编程IC通过包括用户设计和第一测试电路的第一测试设计进行编程，并且运行第一测试模式。可编程IC然后用包括用户设计和第二测试电路的第二测试设计进行编程，并且运行第二测试模式。如果其中一个测试模式失败，另一个测试模式通过，则可编程IC通过测试序列。由于其中一个测试模式已经通过，所以在测试电路中必须出现其他测试模式的错误，这对于可编程IC中用户设计的功能来说是不必要的。因此，一个测试模式的成功表明，有缺陷的资源不包括在用于实现用户设计的可编程IC的部分中。

9. 发明授权

US07315972B1 Method and apparatus for automated generation of expected value data for circuit designs 有权
标题翻译：用于自动生成电路设计的预期值数据的方法和装置
公开(公告)号：US07315972B1
公开(公告)日：2008-01-01
申请号：US10850184
申请日：2004-05-20
申请人： Shekhar Bapat
发明人： Shekhar Bapat
IPC分类号： G01R31/28
CPC分类号： G01R31/318516 , G01R31/318364 , G06F17/5027
摘要： Method and apparatus for generating expected value data for testing a circuit configured in a programmable logic device (PLD). A simulation model is generated from a circuit representation for the circuit. Nodes in the simulation model configured for readback capture are automatically identified. The circuit representation is simulated as defined by the simulation model. Expected value data is recorded during the simulation in response to the identified nodes. A method and apparatus for testing a circuit configured in a PLD is also described. Expected value data for components of a circuit representation for the circuit is automatically generated using a modeling system, where the components are configured for readback capture. A test stimulus is applied to the circuit and state data is captured. The captured state data is compared with the expected value data.
摘要翻译：用于生成用于测试在可编程逻辑器件（PLD）中配置的电路的预期值数据的方法和装置。从电路的电路表示生成仿真模型。自动识别配置为回读捕获的仿真模型中的节点。仿真模拟模拟电路表示。在仿真期间响应于所识别的节点记录期望值数据。还描述了用于测试在PLD中配置的电路的方法和装置。使用建模系统自动生成电路电路表示组件的预期值数据，其中组件配置为进行回读捕获。将测试刺激应用于电路并捕获状态数据。捕获的状态数据与预期值数据进行比较。

10. 发明授权

US07007250B1 Application-specific methods useful for testing look up tables in programmable logic devices 有权
标题翻译：应用程序特定的方法可用于测试可编程逻辑器件中的查找表
公开(公告)号：US07007250B1
公开(公告)日：2006-02-28
申请号：US10388000
申请日：2003-03-12
申请人： Shekhar Bapat , Robert W. Wells , Robert D. Patrie , Andrew W. Lai
发明人： Shekhar Bapat , Robert W. Wells , Robert D. Patrie , Andrew W. Lai
IPC分类号： G06F17/50
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.
摘要翻译：公开的利用包含至少一个局部缺陷的可编程逻辑器件的方法。测试这些设备以确定其适用于实施可能不需要受缺陷影响的资源的所选客户设计。如果发现FPGA不适合于一个设计，则可以测试其他设计。在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。测试电路允许PLD供应商验证PLD对于给定客户设计的适用性，而不要求供应商了解设计。

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