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1. 发明申请

US20140103406A1 SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF FABRICATION THEREOF 有权
标题翻译：具有降低接合漏电的半导体结构及其制造方法
公开(公告)号：US20140103406A1
公开(公告)日：2014-04-17
申请号：US14133743
申请日：2013-12-19
申请人： Lingquan Wang , Teymur Bakhishev , Dalong Zhao , Pushkar Ranade , Sameer Pradhan , Thomas Hoffmann , Lucian Shifren , Lance Scudder
发明人： Lingquan Wang , Teymur Bakhishev , Dalong Zhao , Pushkar Ranade , Sameer Pradhan , Thomas Hoffmann , Lucian Shifren , Lance Scudder
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L21/743 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L27/092 , H01L29/105 , H01L29/66477 , H01L29/6659
摘要： A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.
摘要翻译：半导体结构由NFET器件和PFET器件形成。通过掩蔽衬底的PFET器件区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏蔽层上形成未掺杂沟道层，形成NFET器件。 PFET器件类似地通过掩蔽衬底的NFET区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏幕层上形成未掺杂沟道层。在NFET和PFET器件区域之间形成隔离区以去除在单独外延生长阶段期间发生的任何刻面。通过原位掺杂外延生长形成屏蔽层，相对于使用离子注入形成屏幕层，实现了结漏电减少。

2. 发明授权

US08637955B1 Semiconductor structure with reduced junction leakage and method of fabrication thereof 有权
标题翻译：具有减少结漏电的半导体结构及其制造方法
公开(公告)号：US08637955B1
公开(公告)日：2014-01-28
申请号：US13600647
申请日：2012-08-31
申请人： Lingquan Wang , Teymur Bakhishev , Dalong Zhao , Pushkar Ranade , Sameer Pradhan , Thomas Hoffmann , Lucian Shifren , Lance Scudder
发明人： Lingquan Wang , Teymur Bakhishev , Dalong Zhao , Pushkar Ranade , Sameer Pradhan , Thomas Hoffmann , Lucian Shifren , Lance Scudder
IPC分类号： H01L29/15 , H01L29/167 , H01L29/36
CPC分类号： H01L29/78 , H01L21/743 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L27/092 , H01L29/105 , H01L29/66477 , H01L29/6659
摘要： A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.
摘要翻译：半导体结构由NFET器件和PFET器件形成。通过掩蔽衬底的PFET器件区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏蔽层上形成未掺杂沟道层，形成NFET器件。 PFET器件类似地通过掩蔽衬底的NFET区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏幕层上形成未掺杂沟道层。在NFET和PFET器件区域之间形成隔离区以去除在单独外延生长阶段期间发生的任何刻面。通过通过原位掺杂的外延生长形成屏蔽层，相对于使用离子注入形成屏幕层，实现了结漏电减少。

3. 发明授权

US08569156B1 Reducing or eliminating pre-amorphization in transistor manufacture 有权
公开(公告)号：US08569156B1
公开(公告)日：2013-10-29
申请号：US13473403
申请日：2012-05-16
申请人： Lance Scudder , Pushkar Ranade , Charles Stager , Urupattur C. Sridharan , Dalong Zhao
发明人： Lance Scudder , Pushkar Ranade , Charles Stager , Urupattur C. Sridharan , Dalong Zhao
IPC分类号： H01L21/425 , H01L21/336 , H01L21/36 , H01L21/20
CPC分类号： H01L21/823892 , H01L21/02694 , H01L21/046 , H01L21/26506 , H01L21/8213 , H01L21/823878 , H01L27/0921 , H01L29/105 , H01L29/1083 , H01L29/66068 , H01L29/66537 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

4. 发明申请

US20050016466A1 Susceptor with raised tabs for semiconductor wafer processing 审中-公开
标题翻译：具有用于半导体晶片处理的凸起片的受体
公开(公告)号：US20050016466A1
公开(公告)日：2005-01-27
申请号：US10626174
申请日：2003-07-23
申请人： Lance Scudder , Michael Thompson , Robert Trujillo
发明人： Lance Scudder , Michael Thompson , Robert Trujillo
IPC分类号： C23C16/458 , H01L21/687 , H01L21/31 , C23C16/00 , H01L21/469
CPC分类号： H01L21/68735 , C23C16/4585 , H01L21/6875
摘要： Described is a susceptor with a wafer pocket, to contain a wafer during a wafer processing procedure, and a plurality of raised tabs along the outer perimeter of the wafer pocket that are configured to maintain the wafer in the wafer pocket during wafer processing. The tabs have a tab height that is independent of the pocket depth.
摘要翻译：描述了具有晶片袋的基座，以在晶片处理过程期间容纳晶片，以及沿着晶片槽的外周边的多个凸起突片，其配置成在晶片处理期间将晶片保持在晶片槽中。标签具有独立于凹坑深度的标签高度。

5. 发明授权

US5198071A Process for inhibiting slip and microcracking while forming epitaxial layer on semiconductor wafer 失效
标题翻译：在半导体晶片上形成外延层的同时抑制滑移和微裂纹的方法
公开(公告)号：US5198071A
公开(公告)日：1993-03-30
申请号：US797614
申请日：1991-11-25
申请人： Lance Scudder , Norma Riley
发明人： Lance Scudder , Norma Riley
IPC分类号： C23C16/02 , C23C16/24 , C23C16/56 , C30B25/02 , C30B33/00 , H01L21/205
CPC分类号： C30B29/06 , C23C16/02 , C23C16/24 , C23C16/56 , C30B25/02 , C30B33/00 , H01L21/02381 , H01L21/02532 , H01L21/0262 , Y10S148/017 , Y10S148/024
摘要： A process for the formation of an epitaxial layer on a semiconductor wafer is described which inhibits the formation of thermal stress in the semiconductor wafer such as a silicon wafer, during the formation of such an epitaxial layer thereon. In one aspect, such thermal stress is inhibited during the deposition of the epitaxial material by initially reducing the deposition rate to less than 1 .mu.m per minute or lower until the epitaxial layer reaches a thickness of from about 2 to about 30 .mu.m. In another aspect of the invention, any bridge materials formed between the wafer and the wafer support, during formation of the epitaxial layer, is removed before the wafer is cooled, i.e., before such bridge materials can induce thermal stress in the wafer during the cooling of the wafer, by post etching the wafer with HCl etching gas after the epitaxial deposition.
摘要翻译：描述了在半导体晶片上形成外延层的工艺，其中在其形成这样的外延层期间，其抑制了硅晶片等半导体晶片中的热应力的形成。在一个方面，通过将沉积速率初始降低到小于1微米/分钟或更低直到外延层达到约2至约30微米的厚度，在沉积外延材料期间，这种热应力被抑制。在本发明的另一方面，在形成外延层期间在晶片和晶片支撑件之间形成的任何桥接材料在晶片被冷却之前被移除，即在这种桥接材料可以在冷却期间在晶片中引起热应力之前通过在外延沉积之后用HCl蚀刻气体后蚀刻晶片。

6. 发明授权

US08778786B1 Method for substrate preservation during transistor fabrication 有权
标题翻译：晶体管制造过程中衬底保存的方法
公开(公告)号：US08778786B1
公开(公告)日：2014-07-15
申请号：US13482394
申请日：2012-05-29
申请人： Lance Scudder , Pushkar Ranade , Dalong Zhao , Teymur Bakhishev , Urupattur C. Sridharan , Taiji Ema , Toshifumi Mori , Mitsuaki Hori , Junji Oh , Kazushi Fujita , Yasunobu Torii
发明人： Lance Scudder , Pushkar Ranade , Dalong Zhao , Teymur Bakhishev , Urupattur C. Sridharan , Taiji Ema , Toshifumi Mori , Mitsuaki Hori , Junji Oh , Kazushi Fujita , Yasunobu Torii
IPC分类号： H01L21/425 , H01L21/336 , H01L21/266 , H01L21/311
CPC分类号： H01L21/266 , H01L21/31133 , H01L21/823807 , H01L21/823892 , H01L21/8239 , H01L27/0928
摘要： Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.
摘要翻译：在晶体管器件元件制造期间在衬底中防止硅损失是通过在制造过程中限制光刻胶掩模和化学氧化物层剥离的机会来实现的。这可以通过使用在形成和剥离用于将植入区域识别到衬底中的光致抗蚀剂掩模保留在衬底上的保护层来实现。此外，由于光致抗蚀剂掩模未对准而导致的不期望的返工步骤被消除，或者在器件元件制造过程中不会对来自衬底的硅消耗产生影响。以这种方式，具有相同操作特性和性能的装置元件可以从批量到大量一致地进行。

7. 发明申请

US20070240632A1 Silicon-containing layer deposition with silicon compounds 有权
标题翻译：含硅层沉积与硅化合物
公开(公告)号：US20070240632A1
公开(公告)日：2007-10-18
申请号：US11549033
申请日：2006-10-12
申请人： Kaushal Singh , Paul Comita , Lance Scudder , David Carlson
发明人： Kaushal Singh , Paul Comita , Lance Scudder , David Carlson
IPC分类号： C30B23/00
CPC分类号： C07F7/0896 , C01B33/04 , C01B33/107 , C07F7/12 , C23C16/24 , C23C16/30
摘要： Embodiments of the invention relate to methods for depositing silicon-containing materials on a substrate. In one example, a method for selectively and epitaxially depositing a silicon-containing material is provided which includes positioning and heating a substrate containing a crystalline surface and a non-crystalline surface within a process chamber, exposing the substrate to a process gas containing neopentasilane, and depositing an epitaxial layer on the crystalline surface. In another example, a method for blanket depositing a silicon-containing material is provide which includes positioning and heating a substrate containing a crystalline surface and feature surfaces within a process chamber and exposing the substrate to a process gas containing neopentasilane and a carbon source to deposit a silicon carbide blanket layer across the crystalline surface and the feature surfaces. Generally, the silicon carbide blanket layer contains a silicon carbide epitaxial layer selectively deposited on the crystalline surface.
摘要翻译：本发明的实施例涉及在衬底上沉积含硅材料的方法。在一个实例中，提供了一种用于选择性和外延沉积含硅材料的方法，其包括在处理室内定位和加热含有结晶表面和非结晶表面的基底，将基底暴露于含有新戊硅烷的工艺气体中，以及在所述晶体表面上沉积外延层。在另一个实例中，提供了一种用于覆盖沉积含硅材料的方法，其包括定位和加热含有结晶表面的基底和处理室内的特征表面，并将基底暴露于含有新戊硅烷和碳源的工艺气体沉积跨过结晶表面和特征表面的碳化硅毯层。通常，碳化硅覆盖层包含选择性地沉积在晶体表面上的碳化硅外延层。

8. 发明授权

US06774040B2 Apparatus and method for surface finishing a silicon film 失效
公开(公告)号：US06774040B2
公开(公告)日：2004-08-10
申请号：US10243790
申请日：2002-09-12
申请人： Paul B. Comita , Karin Anna Lena Thilderkvist , Lance Scudder
发明人： Paul B. Comita , Karin Anna Lena Thilderkvist , Lance Scudder
IPC分类号： H01L21302
CPC分类号： H01L21/02046 , C30B29/06 , C30B33/00 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02513 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/67115 , H01L21/76254 , Y10S438/964 , Y10S438/977
摘要： A method of treating a silicon surface of a substrate that includes heating the substrate in a process chamber to a temperature, exposing a first area adjacent to the silicon surface to a first gas mixture comprising an etchant, a silicon source gas, and a carrier, exposing a second area adjacent to the silicon surface to a second gas mixture, wherein the second gas mixture is different from the first gas mixture.

9. 发明授权

US06489241B1 Apparatus and method for surface finishing a silicon film 有权
标题翻译：用于表面处理硅膜的设备和方法
公开(公告)号：US06489241B1
公开(公告)日：2002-12-03
申请号：US09399443
申请日：1999-09-17
申请人： Anna Lena Thilderkvist , Paul Comita , Lance Scudder , Norma Riley
发明人： Anna Lena Thilderkvist , Paul Comita , Lance Scudder , Norma Riley
IPC分类号： H01L21302
CPC分类号： H01L21/02046 , C23C16/0236 , C30B29/06 , C30B33/12 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/30604 , H01L21/3065 , H01L21/31116 , H01L21/67115 , H01L21/67155 , H01L21/76254 , Y10S438/964 , Y10S438/977
摘要： A method of smoothing a silicon surface formed on a substrate. According to the present invention a substrate having a silicon surface is placed into a chamber and heated to a temperature of between 1000°-1300° C. While the substrate is heated to a temperature between 1000°-1300° C., the silicon surface is exposed to a gas mix comprising H2 and HCl in the chamber to smooth the silicon surface.
摘要翻译：一种平滑形成在基底上的硅表面的方法。根据本发明，将具有硅表面的基板放置在室中并加热到1000°-1300℃之间的温度。当将基板加热到1000°-1300℃之间的温度时，硅表面在室内暴露于包含H 2和HCl的气体混合物中以使硅表面平滑。

10. 发明授权

US08796048B1 Monitoring and measurement of thin film layers 有权
标题翻译：监测和测量薄膜层
公开(公告)号：US08796048B1
公开(公告)日：2014-08-05
申请号：US13469598
申请日：2012-05-11
申请人： Scott E. Thompson , Pushkar Ranade , Lance Scudder , Charles Stager
发明人： Scott E. Thompson , Pushkar Ranade , Lance Scudder , Charles Stager
IPC分类号： H01L21/66 , H01L21/67 , H01L21/762
CPC分类号： H01L21/67253 , H01L21/76229 , H01L22/12 , H01L22/30
摘要： The present disclosure provides methods and structures for measurement, control, and monitoring the thickness of thin film layers formed as part of a semiconductor manufacturing process. The methods and structures presented provide the capability to measure and monitor the thickness of the thin film using trench line structures. In certain embodiments, the thin film thickness measurement system can be integrated with thin film growth and control software, providing automated process control (APC) or statistical process control (SPC) capability by measuring and monitoring the thin film thickness during manufacturing. Methods for measuring the thickness of thin films can be important to the fabrication of integrated circuits because the thickness and uniformity of the thin film can determine electrical characteristics of the transistors being fabricated.
摘要翻译：本公开提供了用于测量，控制和监测作为半导体制造工艺的一部分形成的薄膜层的厚度的方法和结构。所提出的方法和结构提供了使用沟槽结构测量和监测薄膜的厚度的能力。在某些实施例中，薄膜厚度测量系统可以与薄膜生长和控制软件集成，通过在制造期间测量和监测薄膜厚度来提供自动化过程控制（APC）或统计过程控制（SPC）能力。用于测量薄膜厚度的方法对于集成电路的制造而言是重要的，因为薄膜的厚度和均匀性可以确定正在制造的晶体管的电特性。

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