专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20010040278A1 Ultra high density integrated circuit BLP stack and method for fabricating the same 失效
标题翻译：超高密度集成电路BLP堆叠及其制造方法
公开(公告)号：US20010040278A1
公开(公告)日：2001-11-15
申请号：US09848586
申请日：2001-05-04
申请人： LG SEMICON CO., LTD.
发明人： Gi Bon Cha , Hee Joong Suh , Chang Kuk Choi
IPC分类号： H01L023/02
CPC分类号： H01L23/4951 , H01L24/48 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2225/1029 , H01L2225/1041 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/3511 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.
摘要翻译： BLP堆叠被公开，其具有更高的可靠性和更少的安装面积，用于提供更密集的封装，包括具有外部电源连接引线的第一封装，每个开关都通过其底部暴露并通过侧面延伸到顶表面底表面上的底引线部分，侧表面上的侧引线部分和顶表面上的上引线部分，并且具有外部电源连接引线的第二封装开始暴露于其底部并与外部接触第一封装上的电连接引线与其电连接。

2. 发明申请

US20010010942A1 Solid state image sensor device and method of fabricating the same 有权
公开(公告)号：US20010010942A1
公开(公告)日：2001-08-02
申请号：US09809284
申请日：2001-03-16
申请人： LG Semicon Co., Ltd.
发明人： Sun Choi
IPC分类号： H01L027/148 , H01L029/768 , H01L021/00 , H01L021/339
CPC分类号： H01L29/76833 , H01L27/14683 , H01L27/14806
摘要： A solid state image sensor device and a method of fabricating the same are disclosed in the present invention. A solid state image sensor device includes a semiconductor substrate, a well region in the semiconductor substrate, a horizontal charge transmission region in the well region, a plurality of insulating layers in the horizontal charge transmission region, a gate insulating layer on the entire surface including the insulating layers, a plurality of first polygates on the gate insulating layer, the first polygates being separated from each other and overlapping a portion of each insulating layer, a plurality of impurity regions in the horizontal charge transmission region at both sides of each first polygate, an interlayer insulating layer on the entire surface including the first polygates, and a plurality of second polygates on the interlayer insulating layer and overlapped with a portion of each first polygate.

3. 发明申请

US20010000914A1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US20010000914A1
公开(公告)日：2001-05-10
申请号：US09736205
申请日：2000-12-15
申请人： LG Semicon Co., Ltd.
发明人： Young June Park , Jong Ho Lee , Hyeok Jae Lee
IPC分类号： H01L047/00 , H01L021/338
CPC分类号： H01L29/66757 , H01L21/764
摘要： A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

4. 发明申请

US20030111696A1 Mask ROM cell and method of fabricating the same 失效
标题翻译：掩模ROM单元及其制造方法
公开(公告)号：US20030111696A1
公开(公告)日：2003-06-19
申请号：US10364399
申请日：2003-02-12
申请人： LG Semicon Co., Ltd.
发明人： Jin Soo Kim
IPC分类号： H01L029/76
CPC分类号： H01L27/1126 , H01L27/112
摘要： Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on the semiconductor substrate, and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.
摘要翻译：掩模ROM单元及其制造方法公开在半导体基板中，在一个方向上形成有第一导电类型的半导体基板和第二导电类型的多个杂质扩散区域，其间具有预定距离，对应于每个杂质扩散区域形成在半导体衬底的一部分上的绝缘层，形成在半导体衬底上的栅极绝缘层和以预定间隔形成在栅极绝缘层和绝缘层上的多个导电线，垂直于杂质扩散区。

5. 发明申请

US20020094630A1 Charge coupled device and method of fabricating the same 有权
标题翻译：电荷耦合器件及其制造方法
公开(公告)号：US20020094630A1
公开(公告)日：2002-07-18
申请号：US10086520
申请日：2002-03-04
申请人： LG Semicon Co., Ltd.
发明人： Seo Kyu Lee
IPC分类号： H01L021/8238 , H01L021/336
CPC分类号： H01L29/42396 , H01L27/14831
摘要： A CCD and method of fabricating the same, which reads signal charges completely and increases the fill factor of its pixel, to improve the sensitivity. The CCD having photodiodes in matrix form, includes a first interlevel insulating layer and first transfer gate sequentially formed between the photodiodes arranged in the row direction, a block insulating layer formed along the center of the first transfer gate, a second interlevel insulating layer formed on the first transfer gate, second and third transfer gates formed on the first transfer gate, being isolated from each other on the block insulating layer, a third interlevel insulating layer formed on the second and third transfer gates, and a fourth transfer gate formed on the third interlevel insulating layer, being placed on the second and third transfer gates.
摘要翻译：一种CCD及其制造方法，其完全读取信号电荷并增加其像素的填充因子，以提高灵敏度。具有矩阵形式的光电二极管的CCD包括顺序地形成在沿行方向布置的光电二极管之间的第一层间绝缘层和第一传输栅极，沿着第一传输栅极的中心形成的块绝缘层，形成在第二层间绝缘层上的第二层间绝缘层形成在第一传输栅极上的第一传输栅极，第二和第三传输栅极在块绝缘层上彼此隔离，形成在第二和第三传输栅极上的第三层间绝缘层和形成在第二传输门上的第四传输栅极第三层间绝缘层，放置在第二和第三传输门上。

6. 发明申请

US20020033710A1 TDDB test pattern and method for testing TDDB of MOS capacitor dielectric 有权
标题翻译： TDDB测试方法和测试方法，用于测量MOS电容电介质的TDDB
公开(公告)号：US20020033710A1
公开(公告)日：2002-03-21
申请号：US09995680
申请日：2001-11-29
申请人： LG Semicon Co., Ltd.
发明人： Ha Zoong Kim
IPC分类号： G01R031/26
CPC分类号： G01R31/129 , G01R31/1227 , G01R31/2623 , G01R31/2639
摘要： A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.
摘要翻译：讨论了一种可以减少测试时间和统计上提高测量精度的时间依赖介质击穿（TDDB）测试图案电路，以及测试图案电路测试方法。通常，测试图案电路包括多个单元测试图案。每个单元测试图案包括连接到应力电压的电容器。应力电压被施加到电容器，并且随着时间的推移测量从电容器流出的电流。电容器中的电介质随时间而分解，在某一点，电容器电流突然变化。不幸的是，会议测试模式电路需要对每个单元进行串行测试，因此当涉及许多单位单元时，测量时间是显着的。电路允许对测试图形电路中的所有单位单元同时进行测量。这大大降低了测试时间，允许获得更大量的数据，从而提高了统计学准确性，并降低了成本。

7. 发明申请

US20010018244A1 Capacitor for semiconductor device and method for manufacturing the same 失效
标题翻译：半导体器件用电容器及其制造方法
公开(公告)号：US20010018244A1
公开(公告)日：2001-08-30
申请号：US09802910
申请日：2001-03-12
申请人： LG Semicon Co., Ltd.
发明人： Won Cheol Cho
IPC分类号： H01L021/8242 , H01L021/20 , H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10852 , H01L28/86
摘要： A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions from therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.
摘要翻译：公开了一种用于半导体器件的电容器，其通过简化的制造工艺产生增加的电容。电容器具有形成在其中具有杂质区的半导体器件上的存储节点电极结构。存储节点电极结构包括形成在由半导体器件限定的存储节点孔中的掩埋层，所述掩埋层与至少一个杂质区相接触，所述掩埋层形成在所述掩埋层上并延伸超过所述掩埋层，第一圆柱形电极具有从底层向上延伸的第一壁，以及第二圆柱形电极，其具有从底层向上延伸并设置在第一圆柱形电极的外侧上的第二壁。

8. 发明申请

US20010012665A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20010012665A1
公开(公告)日：2001-08-09
申请号：US09735909
申请日：2000-12-14
申请人： LG Semicon Co., Ltd.
发明人： Gyu Han Yoon
IPC分类号： H01L021/336
CPC分类号： H01L29/512 , H01L21/2255 , H01L29/1045 , H01L29/1083 , H01L29/66492 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.
摘要翻译：公开了一种半导体器件，包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 形成在所述栅极电极和半导体衬底之间并形成在包括所述栅电极的一个边缘的第一区域的第一栅极绝缘层; 形成在栅电极和半导体衬底之间的第二栅极绝缘层，并且形成在包括栅极电极的另一边缘的第二部分处，第二栅极绝缘层比第一栅极绝缘层厚; 形成在半导体衬底的预定部分中的第一杂质区，放置在栅电极的两侧; 以及形成在所述半导体衬底的预定部分中的第二杂质区，设置在所述第二栅绝缘层的下方。

9. 发明申请

US20010010953A1 Thin film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20010010953A1
公开(公告)日：2001-08-02
申请号：US09810232
申请日：2001-03-19
申请人： LG Semicon Co., Ltd.
发明人： Sung Gu Kang , Young Jun Jeon
IPC分类号： H01L021/00 , H01L021/84
CPC分类号： H01L29/66765 , H01L29/41733 , H01L29/78618 , Y10S438/978
摘要： A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer. First and second conductive materials are deposited on the second semiconductor layer. A single etching process is performed on the first and second conductive materials using the same etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode to make the etched first and second conductive materials have a tier structure at edges of the prescribed part.
摘要翻译：提供一种薄膜晶体管，其包括基板，形成在基板上的栅极电极和形成在包括栅极电极的基板整个上的栅极绝缘层。在栅绝缘层上形成第一半导体层，在第一半导体层上形成第二半导体层。源极和漏极分别被蚀刻在一起以在栅电极上露出第二半导体层的规定部分表面。与第二半导体层的规定部分相邻的源极和漏极在其边缘处非线性倾斜。制造薄膜晶体管的方法包括在基板上形成栅电极; 在所述栅极电极和所述基板上形成栅极绝缘层，在所述栅极绝缘层上形成第一半导体层，并在所述第一半导体层上形成第二半导体层。第一和第二导电材料沉积在第二半导体层上。使用相同的蚀刻气体对第一和第二导电材料进行单蚀刻处理，以在栅电极上露出第二半导体层的规定部分，以使蚀刻的第一和第二导电材料在规定的边缘处具有层结构部分。

10. 发明申请

US20040257107A1 TDDB test pattern and method for testing TDDB of MOS capacitor dielectric 有权
标题翻译： TDDB测试方法和测试方法，用于测量MOS电容电介质的TDDB
公开(公告)号：US20040257107A1
公开(公告)日：2004-12-23
申请号：US10895285
申请日：2004-07-21
申请人： LG SEMICON CO., LTD.
发明人： Ha Zoong Kim
IPC分类号： G01R031/26
CPC分类号： G01R31/129 , G01R31/1227 , G01R31/2623 , G01R31/2639
摘要： A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.
摘要翻译：讨论了一种可以减少测试时间和统计上提高测量精度的时间依赖介质击穿（TDDB）测试图案电路，以及测试图案电路测试方法。通常，测试图案电路包括多个单元测试图案。每个单元测试图案包括连接到应力电压的电容器。应力电压被施加到电容器，并且随着时间的推移测量从电容器流出的电流。电容器中的电介质随时间而分解，在某一点，电容器电流突然变化。不幸的是，会议测试模式电路需要对每个单元进行串行测试，因此当涉及许多单位单元时，测量时间是显着的。电路允许对测试图形电路中的所有单位单元同时进行测量。这大大降低了测试时间，允许获得更大量的数据，从而提高了统计学准确性，并降低了成本。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式