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1. 发明申请

US20040263192A1 Method and apparatus for measuring relative, within-die leakage current and/or providing a temperature variation profile using a leakage inverter and ring oscillator 有权
标题翻译：用于测量相对，管芯内泄漏电流和/或使用泄漏逆变器和环形振荡器提供温度变化曲线的方法和装置
公开(公告)号：US20040263192A1
公开(公告)日：2004-12-30
申请号：US10816018
申请日：2004-03-31
发明人： Marijan Persun , Samie B. Samaan
IPC分类号： G01R031/26
CPC分类号： G01R31/3008
摘要： A leakage inverter has a switching delay in one direction that is directly proportional to the drain or gate leakage current of either an n-type or p-type device. For one aspect, a leakage ring oscillator includes an odd number of inverters including at least one leakage inverter such that the frequency of oscillation of the leakage ring oscillator is directly proportional to local device leakage. For another aspect, a leakage ring oscillator may be used to indicate temperature and/or temperature variation on a die.
摘要翻译：泄漏逆变器具有与n型或p型器件的漏极或漏极电流成正比的一个方向的开关延迟。一方面，泄漏环形振荡器包括奇数个反相器，其包括至少一个泄漏反相器，使得漏磁环振荡器的振荡频率与本地器件泄漏成正比。另一方面，泄漏环形振荡器可用于指示管芯上的温度和/或温度变化。

2. 发明申请

US20040257104A1 Evaluation device for evaluating semiconductor device 失效
标题翻译：用于评估半导体器件的评估装置
公开(公告)号：US20040257104A1
公开(公告)日：2004-12-23
申请号：US10869872
申请日：2004-06-18
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Sugao Fujinaga , Nobuyuki Moriwaki
IPC分类号： G01R031/26
CPC分类号： G11C29/025 , G11C29/02 , H01L2924/0002 , H01L2924/00
摘要： An evaluation device for evaluating a semiconductor device, used for evaluating electric characteristics of an electrical connection member provided in a vertical direction to a substrate surface, includes a unit circuit having a switching transistor in which a gate thereof connected to a signal line and one of a source and a drain thereof is connected to a first interconnect, and a first resistance element in which one terminal is connected to the other one of the source and the drain of the switching transistor and the other terminal is connected to a second interconnect. The first resistance element constituting each unit circuit includes at least one electrical connection member.
摘要翻译：用于评估用于评估在垂直方向上设置在基板表面上的电连接部件的电特性的半导体装置的评估装置包括具有开关晶体管的单元电路，其中连接到信号线的栅极和其源极和漏极连接到第一互连，并且第一电阻元件，其中一个端子连接到开关晶体管的源极和漏极中的另一个，而另一个端子连接到第二互连。构成每个单元电路的第一电阻元件包括至少一个电连接构件。

3. 发明申请

US20040257103A1 MODULE HAVING TEST ARCHITECTURE FOR FACILITATING THE TESTING OF BALL GRID ARRAY PACKAGES, AND TEST METHOD USING THE SAME 失效
标题翻译：具有用于促进球网阵列包装测试的测试架构的模块以及使用其的测试方法
公开(公告)号：US20040257103A1
公开(公告)日：2004-12-23
申请号：US10795507
申请日：2004-03-09
发明人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee
IPC分类号： G01R031/26
CPC分类号： H05K1/0268 , G01R1/0483 , G01R31/31905 , G11C29/48 , G11C2029/5602 , H01L2224/48091 , H01L2224/859 , H01L2924/15311 , H01L2924/3011 , H05K1/111 , H05K2201/10734 , H01L2924/00014
摘要： A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.
摘要翻译：球栅阵列（BGA）封装测试模块包括BGA封装，模块板和测试架构，用于在安装到模块板时测试BGA封装。 BGA封装测试模块的测试架构包括连接到BGA封装的焊球的封装测试信号线，沿BGA封装的底表面延伸，沿着模块板延伸的板测试信号线，以及将封装相互连接的电连接和板测试信号线。来自BGA封装的信号可以由测试装置的探头通过板测试信号线拾取。本发明的优点在于，当存储器模块运行时，其最小化由测试信号线引起的短截线的影响。

4. 发明申请

US20040251924A1 Semiconductor device tester 有权
标题翻译：半导体器件测试仪
公开(公告)号：US20040251924A1
公开(公告)日：2004-12-16
申请号：US10493849
申请日：2004-04-27
发明人： Satoshi Sudou
IPC分类号： G01R031/26
CPC分类号： G01R31/31917 , G01R31/31924 , G01R31/31928
摘要： In a semiconductor device testing apparatus for testing a plurality of semiconductor devices at one time, data peculiar to each semiconductor device can be written therein simultaneously with the avoidance of excessive enlargement in the scale of circuitry. A pair of an integer delay generation part and a fraction delay data generation part that are components of the semiconductor device testing apparatus is provided by the same number as that of pins of each semiconductor device under test, and a waveform control part is provided by the same number as that of the semiconductor devices under test for each of the pairs. In each waveform control part are generated a set pulse and a reset pulse for generating a test pattern signal to be applied to each of pins having the same attribute of the semiconductor devices under test, thereby to generate a test pattern signal. By applying individual data to each waveform control part instead of test pattern data, respective individual data can be written simultaneously in the semiconductor devices under test.
摘要翻译：在一次用于测试多个半导体器件的半导体器件测试装置中，可以同时写入每个半导体器件特有的数据，避免电路规模的过度放大。作为半导体器件测试装置的组成部分的一对整数延迟产生部分和分数延迟数据生成部分被设置成与被测半导体器件的引脚相同的数量，波形控制部分由与对于每个对的被测半导体器件的数量相同。在每个波形控制部分中产生设置脉冲和复位脉冲，用于产生要施加到具有与被测半导体器件相同属性的每个引脚的测试图案信号，从而产生测试图案信号。通过将各个数据应用于每个波形控制部分而不是测试图案数据，可以在被测半导体器件中同时写入各自的数据。

5. 发明申请

US20040239362A1 Input system for an operations circuit 有权
标题翻译：一个操作电路的输入系统
公开(公告)号：US20040239362A1
公开(公告)日：2004-12-02
申请号：US10869976
申请日：2004-06-16
发明人： Troy A. Manning
IPC分类号： G01R031/26
CPC分类号： G01R31/31905 , G01R31/2884 , G06F11/2733
摘要： An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals from the redundant bond pad are biased to ground during normal operations of the integrated device. In order to test the relevant internal circuitry, a voltage is applied to a Test Mode Enable bond pad, overcoming the bias that grounds the redundant bond pad. In addition, the signal from the Test Mode Enable bond pad serves to ground any transmission from the main bond pad. As a result, the redundant bond pad may be used to test the relevant internal circuitry given its accessible location in relation to the testing equipment.
摘要翻译：如果用于该电路的主接合焊盘难以用测试设备访问，则集成设备包括用于访问内部电路的冗余接合焊盘。来自冗余接合焊盘的信号在集成器件的正常操作期间被偏置到接地。为了测试相关的内部电路，将一个电压施加到测试模式使能焊盘，克服接地冗余焊盘的偏压。此外，来自测试模式使能接合焊盘的信号用于接地主接合焊盘的任何传输。因此，冗余接合焊盘可用于测试相对于测试设备的可访问位置的相关内部电路。

6. 发明申请

US20040224427A1 [A DETECTION METHOD FOR METAL CONTAMINATION AND MICRO PARTICLES OF A FABRICATION DEVICE] 审中-公开
标题翻译： [金属污染的检测方法和制造装置的微粒子]
公开(公告)号：US20040224427A1
公开(公告)日：2004-11-11
申请号：US10249757
申请日：2003-05-06
发明人： Wen-Guang Yu , Liang-Tien Huang
IPC分类号： H01L021/66 , G01R031/26
CPC分类号： G01N21/9501 , G01N15/14
摘要： A detection method for metal contamination and micro particles of a fabrication device is disclosed. The method comprises providing a control chip; transferring the control chip to a fabrication device so that the control chip is treated by the fabrication device; removing the control chip from the fabrication device; forming a silicon material layer on the control chip; and measuring the number of particles and defects formed on the silicon material layer of the control chip. Therefore, the extent of metallic contamination and micro particle of the fabrication device can be determined.
摘要翻译：公开了一种制造装置的金属污染物和微粒子的检测方法。该方法包括提供控制芯片; 将控制芯片传送到制造装置，使得控制芯片由制造装置处理; 从制造装置移除控制芯片; 在控制芯片上形成硅材料层; 并测量在控制芯片的硅材料层上形成的颗粒和缺陷的数量。因此，可以确定制造装置的金属污染和微粒子的程度。

7. 发明申请

US20040212390A1 Slope efficiency measurement apparatus for a laser device and method therefor 失效
标题翻译：用于激光装置的斜率效率测量装置及其方法
公开(公告)号：US20040212390A1
公开(公告)日：2004-10-28
申请号：US10722395
申请日：2003-11-28
申请人： AGILENT TECHNOLOGIES, INC.
发明人： Andrew Harker
IPC分类号： G01R031/26
CPC分类号： H01S5/06832 , G01J1/4257 , H01S5/0014
摘要： The slope efficiency of a laser diode is determined by temporarily adjusting a current applied to the laser and measuring a corresponding change in the average output power. Such prior art techniques require the laser modulation current average to be small to avoid impairment of transmission of data by the laser diode. An optical attenuator opposite an output of a laser diode resolves this problem by maintaining the average power emitted by the laser diode within acceptable operating limits.
摘要翻译：激光二极管的斜率效率通过临时调整施加到激光器的电流并测量平均输出功率的相应变化来确定。这种现有技术要求激光调制电流平均值小，以避免由激光二极管传输数据的损害。与激光二极管的输出相对的光衰减器通过将激光二极管发射的平均功率保持在可接受的工作限度内解决了这个问题。

8. 发明申请

US20040212376A1 Space-saving test structures having improved capabilities 失效
标题翻译：具有改进能力的节省空间的测试结构
公开(公告)号：US20040212376A1
公开(公告)日：2004-10-28
申请号：US10423197
申请日：2003-04-25
申请人： Advanced Micro Devices, Inc.
发明人： Hyeon-Seag Kim
IPC分类号： G01R031/26
CPC分类号： G01R31/2858 , G01R31/2831 , G01R31/2884
摘要： A space-saving test structure includes a core metal line, at least one extrusion detection line and an extrusion monitoring segment. The core metal line has a nullnon-linear configurationnull and is capable of conducting current for an electromigration test, an isothermal test, and extrusion monitoring. The at least one extrusion detection line is situated adjacent to the core metal line. The extrusion monitoring segment is electrically connected to the at least one extrusion detection line. The extrusion monitoring segment is adapted to determine whether an extrusion occurs in the core metal line by measuring a resistance between the core metal line and the at least one extrusion detection line.
摘要翻译：节省空间的测试结构包括芯金属线，至少一个挤出检测线和挤出监测段。核心金属线具有“非线性构造”，能够进行电迁移试验，等温试验和挤出监测。至少一个挤出检测线位于与芯金属线相邻的位置。挤出监测段与至少一个挤出检测线电连接。挤出监测段适于通过测量芯金属线和至少一个挤出检测线之间的电阻来确定是否在芯金属线中发生挤压。

9. 发明申请

US20040207387A1 Method for electrical testing of semiconductor package that detects socket defects in real time 有权
标题翻译：实时检测插座缺陷的半导体封装的电气测试方法
公开(公告)号：US20040207387A1
公开(公告)日：2004-10-21
申请号：US10824220
申请日：2004-04-13
发明人： Ae-yong Chung , Sung-Ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
IPC分类号： G01R031/26
CPC分类号： G11C29/56016 , G01R31/2893 , G01R31/2894 , G11C2029/5602
摘要： An electrical testing method for a semiconductor package for detecting defects of sockets mounted on a device under test (DUT) board is provided. A tester performs electrical test, accumulates electrical test results, and compares the accumulated results to reference values. The result of the comparison decides whether a plurality of sockets mounted on the DUT board can be used or not. The decision results are transmitted to a handler so that the socket having the defects is not used on the DUT board.
摘要翻译：提供了一种用于检测安装在被测设备（DUT）板上的插座的缺陷的半导体封装的电气测试方法。测试仪进行电气测试，累积电气测试结果，并将累积结果与参考值进行比较。比较结果决定了是否可以使用安装在DUT板上的多个插槽。决定结果被传送到处理器，以便在DUT板上不使用具有缺陷的插座。

10. 发明申请

US20040201396A1 Floating interposer 失效
公开(公告)号：US20040201396A1
公开(公告)日：2004-10-14
申请号：US10832845
申请日：2004-04-27
发明人： Mark Vincent Pierson , Jennifer Rebecca Sweterlitsch , Charles Gerard Woychik , Thurston Bryce Youngs JR.
IPC分类号： G01R031/26
CPC分类号： H01R12/52 , H01L23/49827 , H01L2924/0002 , H01R12/57 , H01R13/2414 , H05K3/3436 , H05K3/42 , H05K7/1061 , H05K13/0465 , H05K2201/0133 , H05K2201/09836 , H05K2201/10378 , Y02P70/613 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

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