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1. 发明授权

US09335805B2 Method and apparatus for managing power in a multi-core processor 有权
标题翻译：在多核处理器中管理电源的方法和装置
公开(公告)号：US09335805B2
公开(公告)日：2016-05-10
申请号：US13989280
申请日：2010-11-25
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/26 , G06F1/32 , G06F9/50
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
摘要翻译：提供了一种在具有两个或多个处理核心的多核数据处理系统中管理电力的方法，包括确定多核处理单元内的两个或多个处理核心的使用特性，并且取决于确定的使用特性，适应提供给两个或多个处理核心中的每一个的频率或电压，和/或调整提供给两个或多个处理核心中的每一个的启用信号。还提供了一种用于实施所公开的方法的装置。

2. 发明申请

US20150331466A1 METHOD AND APPARATUS FOR MANAGING A THERMAL BUDGET OF AT LEAST A PART OF A PROCESSING SYSTEM 有权
标题翻译：用于管理至少一个处理系统的一部分的热预算的方法和装置
公开(公告)号：US20150331466A1
公开(公告)日：2015-11-19
申请号：US14410146
申请日：2012-07-03
申请人： ANTON ROZEN , ROY DRUCKER , LEONID SMOLYANSKY
发明人： ANTON ROZEN , ROY DRUCKER , LEONID SMOLYANSKY
IPC分类号： G06F1/28 , G06F9/46
CPC分类号： G06F1/28 , G06F1/3206 , G06F9/466
摘要： A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.
摘要翻译：描述了对于处理系统的至少一部分来管理热预算的方法。该方法包括：在检测到用例事件之后，确定处理系统的至少一部分的当前用例场景的热预算违反时间窗口，以及基于处理系统的至少部分的热预算管理至少部分地基于确定的热预算违规时间窗口。

3. 发明授权

US08171187B2 System and method for arbitrating between memory access requests 有权
标题翻译：在内存访问请求之间进行仲裁的系统和方法
公开(公告)号：US08171187B2
公开(公告)日：2012-05-01
申请号：US12179799
申请日：2008-07-25
申请人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
IPC分类号： G06F3/00
CPC分类号： G06F13/1605 , Y02D10/14
摘要： A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
摘要翻译：一种具有存储器访问能力的系统，该系统包括：（i）动态电压和频率缩放（DVFS）控制器，适于确定提供给第一存储器访问请求者的电压电平的电平和提供给所述第一存储器访问请求器并且生成指示所述确定的DVFS指示; （ii）硬件访问请求确定模块，用于响应于所述DVFS指示确定由所述第一存储器访问请求者发出的存储器访问请求的优先级; 以及（iii）直接存储器访问仲裁器，适于响应于与所述存储器访问请求相关联的优先级，在由所述第一存储器访问请求者发出的存储器访问请求与另一存储器访问请求者之间进行仲裁。

4. 发明申请

US20150324287A1 A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS 审中-公开
标题翻译：一种使用CPU缓存存储器进行非CPU相关任务的方法和装置
公开(公告)号：US20150324287A1
公开(公告)日：2015-11-12
申请号：US14655109
申请日：2013-01-09
申请人： Michael PRIEL , Yossi AMON , Boris SHULMAN , Leonid SMOLYANSKY , Michael ZARUBINSKY
发明人： MICHAEL PRIEL , YOSSI AMON , BORIS SHULMAN , LEONID SMOLYANSKY , MICHAEL ZARUBINSKY
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0897 , G06F2212/1052 , G06F2212/251 , G06F2212/6012 , Y02D10/13
摘要： There is provided a processor for use in a computing system, said processor including at least one Central Processing Unit (CPU), a cache memory coupled to the at least one CPU, and a control unit coupled to the cache memory and arranged to obscure the existing data in the CPU cache memory, and assign control of the CPU cache memory to at least one other entity within the computing system. There is also provided a method of using a CPU cache memory for non-CPU related tasks in a computing system.
摘要翻译：提供了一种用于计算系统的处理器，所述处理器包括至少一个中央处理单元（CPU），耦合到至少一个CPU的高速缓存存储器，以及耦合到高速缓存存储器并被布置成遮蔽 CPU高速缓冲存储器中的现有数据，并且将CPU缓存存储器的控制分配给计算系统内的至少一个其他实体。还提供了在计算系统中使用用于非CPU相关任务的CPU高速缓冲存储器的方法。

5. 发明申请

US20090177903A1 METHOD AND DEVICE FOR POWER MANAGEMENT 有权
标题翻译：用于电源管理的方法和装置
公开(公告)号：US20090177903A1
公开(公告)日：2009-07-09
申请号：US12304854
申请日：2006-06-22
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.
摘要翻译：一种用于电源管理的设备和方法。该方法包括接收关于电路的负载的指示，在至少一个长时间段期间根据电路负载模式确定至少一个长期激活参数; 响应于所述电路的期望的短周期负载变化来确定至少一个短期激活参数; 以及响应于所述长期激活参数和响应于所述短期供应参数而提供至少一个时钟信号和至少一个电源电压。

6. 发明申请

US20090015232A1 METHOD AND DEVICE FOR REGULATING A VOLTAGE SUPPLY TO A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于调节电压到半导体器件的方法和装置
公开(公告)号：US20090015232A1
公开(公告)日：2009-01-15
申请号：US10595908
申请日：2004-11-18
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky , Boris Bobrov
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky , Boris Bobrov
IPC分类号： G05B24/02
CPC分类号： G06F1/324 , G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device for regulating a voltage supply to a semiconductor device, the device comprising memory for storing a plurality of performance ranges, wherein the respective performance ranges are associated with a respective supply voltage; means for measuring the performance of the semiconductor device; and a regulator for modifying the supply voltage to the semiconductor device if the measured performance of the semiconductor device is not within a predetermined portion of the performance range associated with the voltage supplied to the semiconductor device.
摘要翻译：一种用于调节对半导体器件的电压供应的装置，所述装置包括用于存储多个性能范围的存储器，其中各个性能范围与相应的电源电压相关联; 用于测量半导体器件的性能的装置; 以及如果半导体器件的测量性能不在与提供给半导体器件的电压相关联的性能范围的预定部分内，则修改对半导体器件的电源电压的调节器。

7. 发明申请

US20080256551A1 System and Method For Storing State Information 审中-公开
标题翻译：用于存储状态信息的系统和方法
公开(公告)号：US20080256551A1
公开(公告)日：2008-10-16
申请号：US12067587
申请日：2005-09-21
申请人： Michael Priel , Dan Kuzmin , Leonid Smolyansky
发明人： Michael Priel , Dan Kuzmin , Leonid Smolyansky
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.
摘要翻译：一种用于存储状态信息的方法，所述方法包括在第一电路处存储表示第二电路的状态的状态信息，同时第二电路进入低功率模式; 其特征在于接收从第一任务切换到第二任务的任务应发生的指示; 在所述第一电路处存储表示所述第二电路的状态的状态信息; 收到第一个任务应恢复的指示; 以及将所存储的状态信息从第一电路写入第二电路。一种系统包括第一电路和第二电路，而第一电路连接到第二电路，并适于存储表示第二电路的状态的状态信息; 其特征在于包括控制器，其适于在所述第二电路的至少一部分断电或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。

8. 发明授权

US09841977B2 Processor core arrangement, computing system and methods for designing and operating a processor core arrangement 有权
公开(公告)号：US09841977B2
公开(公告)日：2017-12-12
申请号：US14646988
申请日：2012-11-22
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky , Sergey Sofer
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky , Sergey Sofer
IPC分类号： G06F17/50 , G06F9/30 , G06F1/32 , G06F9/28 , G06F9/48
CPC分类号： G06F9/30189 , G06F1/324 , G06F9/28 , G06F9/48 , G06F17/5045 , G06F2217/68 , G06F2217/78 , Y02D10/126
摘要： The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

9. 发明授权

US08706928B2 Integrated circuit and method for reducing violations of a timing constraint 有权
标题翻译：用于减少违反定时约束的集成电路和方法
公开(公告)号：US08706928B2
公开(公告)日：2014-04-22
申请号：US13504737
申请日：2009-11-26
申请人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
发明人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/1673 , G06F13/1605
摘要： An integrated circuit comprises a shared resource for providing data to a buffer. The buffer is coupled to a buffer level monitor and a filling circuit. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition involving the monitored level of data in the buffer indicates an anticipated violation of a timing constraint.
摘要翻译：集成电路包括用于向缓冲器提供数据的共享资源。缓冲器耦合到缓冲液位监视器和充电电路。访问请求电路耦合到共享资源，用于当访问请求电路访问共享资源时从共享资源接收数据。仲裁器耦合到共享资源，填充电路和访问请求电路，用于从填充电路和访问请求电路接收访问请求，并且向所选共享资源授予对共享资源的访问权限。控制器耦合到缓冲器级监视器和访问请求电路，用于当涉及缓冲器中监视的数据级别的条件指示预期时，访问请求电路降低发送到仲裁器的访问请求的速率违反时间限制。

10. 发明授权

US08462818B2 Method for processing CDMA signals and a device having CDMA signal capabilities 有权
标题翻译：用于处理CDMA信号的方法和具有CDMA信号能力的设备
公开(公告)号：US08462818B2
公开(公告)日：2013-06-11
申请号：US12375796
申请日：2006-08-02
申请人： Michael Zarubinsky , Boris Beri , Boaz Perlman , Leonid Smolyansky , Alexander Sverdlov
发明人： Michael Zarubinsky , Boris Beri , Boaz Perlman , Leonid Smolyansky , Alexander Sverdlov
IPC分类号： H04J13/00
CPC分类号： H04B1/7117 , H04B2201/7071
摘要： A device and a method for processing CDMA compliant signals. The method includes receiving input signals; selecting, for each time interval out of multiple evenly length successive time intervals, multiple selected channel processing tasks that are scheduled to be at least partially executed during the time interval; storing input data at a first input buffer and providing data associated with at least one selected processing task from a second input buffer during even time intervals; and storing input data at the second input buffer and providing data associated with at least one selected processing task from the first input buffer during odd time intervals.
摘要翻译：一种用于处理CDMA兼容信号的装置和方法。该方法包括接收输入信号; 在多个均匀长度的连续时间间隔内为每个时间间隔选择被调度为在该时间间隔期间至少部分地执行的多个选定的信道处理任务; 在第一输入缓冲器处存储输入数据，并且在偶数时间间隔期间从第二输入缓冲器提供与至少一个所选择的处理任务相关联的数据; 以及在第二输入缓冲器处存储输入数据，并且在奇数时间间隔期间从第一输入缓冲器提供与至少一个选择的处理任务相关联的数据。

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