专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120226833A1 INTEGRATED CIRCUIT AND METHOD FOR REDUCING VIOLATIONS OF A TIMING COSTRAINT 有权
标题翻译：集成电路和减少时序成本的冲突的方法
公开(公告)号：US20120226833A1
公开(公告)日：2012-09-06
申请号：US13504737
申请日：2009-11-26
申请人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
发明人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
IPC分类号： G06F5/12
CPC分类号： G06F13/1673 , G06F13/1605
摘要： An integrated circuit and a method for reducing violations of a timing constraint. The integrated circuit comprises a shared resource for providing data and a buffer for storing data. A buffer level monitor is coupled to the buffer, for monitoring a monitored level of data in the buffer. A retrieving circuit is coupled to the buffer, for retrieving the data from the buffer, according to a timing constraint. A filling circuit is coupled to the buffer for writing the data to the buffer and coupled to the shared resource for receiving the data from the shared resource when the filling circuit has access to the shared resource. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition indicating an anticipated violation of the timing constraint is fulfilled, the condition at least involving the monitored level of data in the buffer.
摘要翻译：一种用于减少违反定时约束的集成电路和方法。集成电路包括用于提供数据的共享资源和用于存储数据的缓冲器。缓冲器级监视器耦合到缓冲器，用于监视缓冲器中监视的数据级别。检索电路耦合到缓冲器，用于根据时序约束从缓冲器检索数据。填充电路耦合到缓冲器，用于将数据写入缓冲器并耦合到共享资源，用于当填充电路访问共享资源时从共享资源接收数据。访问请求电路耦合到共享资源，用于当访问请求电路访问共享资源时从共享资源接收数据。仲裁器耦合到共享资源，填充电路和访问请求电路，用于从填充电路和访问请求电路接收访问请求，并且向所选共享资源授予对共享资源的访问权限。控制器耦合到缓冲器级监视器和访问请求电路，用于使得访问请求电路当指示预期违反时序约束的条件得到满足时，降低发送给仲裁器的访问请求的速率，条件至少涉及缓冲区中监视的数据级别。

2. 发明授权

US08706928B2 Integrated circuit and method for reducing violations of a timing constraint 有权
标题翻译：用于减少违反定时约束的集成电路和方法
公开(公告)号：US08706928B2
公开(公告)日：2014-04-22
申请号：US13504737
申请日：2009-11-26
申请人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
发明人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/1673 , G06F13/1605
摘要： An integrated circuit comprises a shared resource for providing data to a buffer. The buffer is coupled to a buffer level monitor and a filling circuit. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition involving the monitored level of data in the buffer indicates an anticipated violation of a timing constraint.
摘要翻译：集成电路包括用于向缓冲器提供数据的共享资源。缓冲器耦合到缓冲液位监视器和充电电路。访问请求电路耦合到共享资源，用于当访问请求电路访问共享资源时从共享资源接收数据。仲裁器耦合到共享资源，填充电路和访问请求电路，用于从填充电路和访问请求电路接收访问请求，并且向所选共享资源授予对共享资源的访问权限。控制器耦合到缓冲器级监视器和访问请求电路，用于当涉及缓冲器中监视的数据级别的条件指示预期时，访问请求电路降低发送到仲裁器的访问请求的速率违反时间限制。

3. 发明申请

US20100023653A1 SYSTEM AND METHOD FOR ARBITRATING BETWEEN MEMORY ACCESS REQUESTS 有权
标题翻译：在存储器访问请求之间进行仲裁的系统和方法
公开(公告)号：US20100023653A1
公开(公告)日：2010-01-28
申请号：US12179799
申请日：2008-07-25
申请人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
IPC分类号： G06F12/00 , G06F13/28 , G06F1/08
CPC分类号： G06F13/1605 , Y02D10/14
摘要： A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
摘要翻译：一种具有存储器访问能力的系统，该系统包括：（i）动态电压和频率缩放（DVFS）控制器，适于确定提供给第一存储器访问请求者的电压电平的电平和提供给所述第一存储器访问请求器并且生成指示所述确定的DVFS指示; （ii）硬件访问请求确定模块，用于响应于所述DVFS指示确定由所述第一存储器访问请求者发出的存储器访问请求的优先级; 以及（iii）直接存储器访问仲裁器，适于响应于与所述存储器访问请求相关联的优先级，在由所述第一存储器访问请求者发出的存储器访问请求与另一存储器访问请求者之间进行仲裁。

4. 发明授权

US08171187B2 System and method for arbitrating between memory access requests 有权
标题翻译：在内存访问请求之间进行仲裁的系统和方法
公开(公告)号：US08171187B2
公开(公告)日：2012-05-01
申请号：US12179799
申请日：2008-07-25
申请人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
IPC分类号： G06F3/00
CPC分类号： G06F13/1605 , Y02D10/14
摘要： A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
摘要翻译：一种具有存储器访问能力的系统，该系统包括：（i）动态电压和频率缩放（DVFS）控制器，适于确定提供给第一存储器访问请求者的电压电平的电平和提供给所述第一存储器访问请求器并且生成指示所述确定的DVFS指示; （ii）硬件访问请求确定模块，用于响应于所述DVFS指示确定由所述第一存储器访问请求者发出的存储器访问请求的优先级; 以及（iii）直接存储器访问仲裁器，适于响应于与所述存储器访问请求相关联的优先级，在由所述第一存储器访问请求者发出的存储器访问请求与另一存储器访问请求者之间进行仲裁。

5. 发明授权

US10268618B2 Chip level switching for multiple computing device interfaces 有权
公开(公告)号：US10268618B2
公开(公告)日：2019-04-23
申请号：US14688350
申请日：2015-04-16
申请人： Dror Geva , Eyal Liser , Roman Mostinski
发明人： Dror Geva , Eyal Liser , Roman Mostinski
IPC分类号： G06F13/40 , G06F13/42 , G06F13/36
摘要： Various semiconductor chips and computing devices are disclosed. In one aspect a semiconductor chip is provided that includes a first interface controller, a first physical layer connected to the first interface controller, a second interface controller, a second physical layer connected to the second interface controller, and a switch connected between the first interface controller and the second interface controller and the first physical layer and the second physical layer. The switch is operable in one mode to route signals to/from the first interface controller via the first physical layer and route signals to/from the second interface controller via the second physical layer and in another mode to route signals to/from both the first interface controller and the second interface controller via the first physical layer.

6. 发明授权

US09906355B2 On-die signal measurement circuit and method 有权
公开(公告)号：US09906355B2
公开(公告)日：2018-02-27
申请号：US14758973
申请日：2013-01-09
申请人： Michael Priel , Leonid Fleshel , Roman Mostinski , Vladimir Nusimovich
发明人： Michael Priel , Leonid Fleshel , Roman Mostinski , Vladimir Nusimovich
IPC分类号： H04L7/00 , G11C19/00 , G01R31/317 , G01R31/28
CPC分类号： H04L7/00 , G01R31/2837 , G01R31/2884 , G01R31/31712 , G11C19/00
摘要： There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

7. 发明申请

US20100073388A1 UNIFIED MEMORY ARCHITECTURE AND DISPLAY CONTROLLER TO PREVENT DATA FEED UNDER-RUN 有权
标题翻译：统一的存储器架构和显示控制器，用于防止数据馈送不足
公开(公告)号：US20100073388A1
公开(公告)日：2010-03-25
申请号：US12596235
申请日：2007-04-26
申请人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
发明人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G09G5/363 , G09G5/397 , G09G2340/02 , G09G2360/125
摘要： A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterised in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterised in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.
摘要翻译：一种显示控制器，用于控制发生数据馈送等待时间波动的同步显示中的数据，所述显示控制器包括接收像素数据并通过主路线和次路径发送像素数据的输入存储器; 其中像素数据通过主路由发送并被处理以预定方式传送到显示器; 其特征在于，所述次路径包括用于存储所述像素数据的二维部分的存储器，所述二维部分至少部分地对应于当时通过所述主路线传输的像素数据; 其特征还在于，所述显示控制器包括用于识别数据馈送等待时间事件的检测器，并且响应于将所述像素数据的传输切换到所述辅助路由并通过辅助路由处理所述像素数据以传送到所述显示器，使得当数据馈送等待时间事件发生在二维路由的像素数据的存储二维部分显示在显示器上。

8. 发明申请

US20080204481A1 Device and Method for Controlling a Backlit Display 审中-公开
标题翻译：用于控制背光显示器的装置和方法
公开(公告)号：US20080204481A1
公开(公告)日：2008-08-28
申请号：US11911929
申请日：2005-04-20
申请人： Roman Mostinski
发明人： Roman Mostinski
IPC分类号： G09G5/02 , G09G3/36
CPC分类号： G09G3/36 , G09G3/3406 , G09G5/393 , G09G2320/041 , G09G2320/0613 , G09G2320/0626 , G09G2320/0646 , G09G2320/066 , G09G2330/021 , G09G2360/144 , G09G2360/16
摘要： A device and method for controlling a display. The method includes: receiving image data, determining backlight illumination intensity in response to an allowed image degradation level parameter and to ambient light, and determining a display refresh parameter in response to a temperature parameter.A method and device for controlling a display, the device includes: a frame buffer adapted to receive image data, a processor adapted to receive a power parameter and an allowed image degradation level parameter, and an image converter that is adapted to perform a linear image conversion and a non-linear image conversion. The processor is adapted to determine which conversion to perform in response to a power parameter.
摘要翻译：一种用于控制显示器的装置和方法。该方法包括：接收图像数据，响应于允许的图像劣化水平参数和环境光确定背光照明强度，以及响应于温度参数确定显示刷新参数。一种用于控制显示器的方法和装置，所述装置包括：适于接收图像数据的帧缓冲器，适于接收功率参数和允许的图像劣化水平参数的处理器，以及适于执行线性图像的图像转换器转换和非线性图像转换。处理器适于确定响应于功率参数而执行的转换。

9. 发明申请

US20160306763A1 CHIP LEVEL SWITCHING FOR MULTIPLE COMPUTING DEVICE INTERFACES 审中-公开
标题翻译：用于多个计算机设备接口的芯片电平切换
公开(公告)号：US20160306763A1
公开(公告)日：2016-10-20
申请号：US14688350
申请日：2015-04-16
申请人： Dror Geva , Eyal Liser , Roman Mostinski
发明人： Dror Geva , Eyal Liser , Roman Mostinski
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/36 , G06F13/4282 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： Various semiconductor chips and computing devices are disclosed. In one aspect a semiconductor chip is provided that includes a first interface controller, a first physical layer connected to the first interface controller, a second interface controller, a second physical layer connected to the second interface controller, and a switch connected between the first interface controller and the second interface controller and the first physical layer and the second physical layer. The switch is operable in one mode to route signals to/from the first interface controller via the first physical layer and route signals to/from the second interface controller via the second physical layer and in another mode to route signals to/from both the first interface controller and the second interface controller via the first physical layer.
摘要翻译：公开了各种半导体芯片和计算设备。在一个方面，提供一种半导体芯片，其包括第一接口控制器，连接到第一接口控制器的第一物理层，第二接口控制器，连接到第二接口控制器的第二物理层，以及连接在第一接口控制器和第二接口控制器以及第一物理层和第二物理层。该开关在一种模式中可操作以经由第一物理层将信号路由到第一接口控制器，并且经由第二物理层将信号路由到第二接口控制器，并且在另一模式中将信号路由到第二接口控制器，接口控制器和第二接口控制器。

10. 发明授权

US08462141B2 Unified memory architecture and display controller to prevent data feed under-run 有权
标题翻译：统一的内存架构和显示控制器，防止数据馈送不足
公开(公告)号：US08462141B2
公开(公告)日：2013-06-11
申请号：US12596235
申请日：2007-04-26
申请人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
发明人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
IPC分类号： G06F3/038 , G06F15/16 , G09G5/36
CPC分类号： G09G5/363 , G09G5/397 , G09G2340/02 , G09G2360/125
摘要： A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterized in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterized in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.
摘要翻译：一种显示控制器，用于控制发生数据馈送等待时间波动的同步显示中的数据，所述显示控制器包括接收像素数据并通过主路线和次路径发送像素数据的输入存储器; 其中像素数据通过主路由发送并被处理以预定方式传送到显示器; 其特征在于，所述次路径包括用于存储所述像素数据的二维部分的存储器，所述二维部分至少部分地对应于当时通过所述主路线传输的像素数据; 其特征还在于，所述显示控制器包括用于识别数据馈送等待时间事件的检测器，并且响应于将所述像素数据的传输切换到所述辅助路由并通过辅助路由处理所述像素数据以传送到所述显示器，使得当数据馈送等待时间事件发生在二维路由的像素数据的存储二维部分显示在显示器上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式