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1. 发明申请

US20090015232A1 METHOD AND DEVICE FOR REGULATING A VOLTAGE SUPPLY TO A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于调节电压到半导体器件的方法和装置
公开(公告)号：US20090015232A1
公开(公告)日：2009-01-15
申请号：US10595908
申请日：2004-11-18
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky , Boris Bobrov
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky , Boris Bobrov
IPC分类号： G05B24/02
CPC分类号： G06F1/324 , G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device for regulating a voltage supply to a semiconductor device, the device comprising memory for storing a plurality of performance ranges, wherein the respective performance ranges are associated with a respective supply voltage; means for measuring the performance of the semiconductor device; and a regulator for modifying the supply voltage to the semiconductor device if the measured performance of the semiconductor device is not within a predetermined portion of the performance range associated with the voltage supplied to the semiconductor device.
摘要翻译：一种用于调节对半导体器件的电压供应的装置，所述装置包括用于存储多个性能范围的存储器，其中各个性能范围与相应的电源电压相关联; 用于测量半导体器件的性能的装置; 以及如果半导体器件的测量性能不在与提供给半导体器件的电压相关联的性能范围的预定部分内，则修改对半导体器件的电源电压的调节器。

2. 发明授权

US09335805B2 Method and apparatus for managing power in a multi-core processor 有权
标题翻译：在多核处理器中管理电源的方法和装置
公开(公告)号：US09335805B2
公开(公告)日：2016-05-10
申请号：US13989280
申请日：2010-11-25
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/26 , G06F1/32 , G06F9/50
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
摘要翻译：提供了一种在具有两个或多个处理核心的多核数据处理系统中管理电力的方法，包括确定多核处理单元内的两个或多个处理核心的使用特性，并且取决于确定的使用特性，适应提供给两个或多个处理核心中的每一个的频率或电压，和/或调整提供给两个或多个处理核心中的每一个的启用信号。还提供了一种用于实施所公开的方法的装置。

3. 发明授权

US08171187B2 System and method for arbitrating between memory access requests 有权
标题翻译：在内存访问请求之间进行仲裁的系统和方法
公开(公告)号：US08171187B2
公开(公告)日：2012-05-01
申请号：US12179799
申请日：2008-07-25
申请人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
IPC分类号： G06F3/00
CPC分类号： G06F13/1605 , Y02D10/14
摘要： A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
摘要翻译：一种具有存储器访问能力的系统，该系统包括：（i）动态电压和频率缩放（DVFS）控制器，适于确定提供给第一存储器访问请求者的电压电平的电平和提供给所述第一存储器访问请求器并且生成指示所述确定的DVFS指示; （ii）硬件访问请求确定模块，用于响应于所述DVFS指示确定由所述第一存储器访问请求者发出的存储器访问请求的优先级; 以及（iii）直接存储器访问仲裁器，适于响应于与所述存储器访问请求相关联的优先级，在由所述第一存储器访问请求者发出的存储器访问请求与另一存储器访问请求者之间进行仲裁。

4. 发明申请

US20090177903A1 METHOD AND DEVICE FOR POWER MANAGEMENT 有权
标题翻译：用于电源管理的方法和装置
公开(公告)号：US20090177903A1
公开(公告)日：2009-07-09
申请号：US12304854
申请日：2006-06-22
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.
摘要翻译：一种用于电源管理的设备和方法。该方法包括接收关于电路的负载的指示，在至少一个长时间段期间根据电路负载模式确定至少一个长期激活参数; 响应于所述电路的期望的短周期负载变化来确定至少一个短期激活参数; 以及响应于所述长期激活参数和响应于所述短期供应参数而提供至少一个时钟信号和至少一个电源电压。

5. 发明授权

US09841977B2 Processor core arrangement, computing system and methods for designing and operating a processor core arrangement 有权
公开(公告)号：US09841977B2
公开(公告)日：2017-12-12
申请号：US14646988
申请日：2012-11-22
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky , Sergey Sofer
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky , Sergey Sofer
IPC分类号： G06F17/50 , G06F9/30 , G06F1/32 , G06F9/28 , G06F9/48
CPC分类号： G06F9/30189 , G06F1/324 , G06F9/28 , G06F9/48 , G06F17/5045 , G06F2217/68 , G06F2217/78 , Y02D10/126
摘要： The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

6. 发明申请

US20130132753A1 INFORMATION PROCESSING DEVICE AND METHOD 有权
标题翻译：信息处理装置和方法
公开(公告)号：US20130132753A1
公开(公告)日：2013-05-23
申请号：US13634999
申请日：2010-06-11
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G01R31/318536 , G01R31/318558 , G06F1/3203 , G06F1/3287 , G06F11/1402 , Y02D10/14 , Y02D10/171
摘要： An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units.
摘要翻译：信息处理设备包括第一存储器，第二存储器，数据传输电路，电源门控电路和控制器。第一存储器包括至少两个易失性存储器单元。控制器接收或产生将信息处理设备设置为降低功率模式的请求; 响应于该请求，它选择存储单元中的特定存储单元; 控制数据传输电路将数据从所选择的存储器单元传送到第二存储器; 并控制电源门控电路使所选存储单元断电。

7. 发明申请

US20130124800A1 APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY 审中-公开
标题翻译：减少处理器延迟的装置和方法
公开(公告)号：US20130124800A1
公开(公告)日：2013-05-16
申请号：US13812168
申请日：2010-07-27
申请人： Michael Priel , Dan Kuzmin , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Dan Kuzmin , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0877 , G06F13/28
摘要： There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to load data directly from the external connection into the processor cache memory and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit operably coupled to a processor cache memory and an external connection operably coupled to the central processing unit and processor cache memory, comprising loading data directly from the external connection into the processor cache memory and modifying a source address for said data to become indicative of a location other than from the external connection.
摘要翻译：提供了一种数据处理系统，包括中央处理单元，可操作地耦合到中央处理单元的处理器高速缓冲存储器和可操作地耦合到中央处理单元和处理器高速缓存存储器的外部连接，其中数据处理系统的一部分被布置将数据直接从外部连接加载到处理器高速缓冲存储器中，并修改所述直接加载数据的源地址。还提供了一种改进数据处理系统中的等待时间的方法，该系统具有可操作地耦合到处理器高速缓冲存储器的中央处理单元和可操作地耦合到中央处理器和处理器高速缓存存储器的外部连接，包括直接从外部连接进入处理器高速缓冲存储器并修改所述数据的源地址以变成指示来自外部连接的位置。

8. 发明申请

US20140325183A1 INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开
标题翻译：集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法
公开(公告)号：US20140325183A1
公开(公告)日：2014-10-30
申请号：US14358053
申请日：2011-11-28
申请人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
摘要翻译：描述了一种非对称多核处理模块。非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其它类型的至少一个处理核心的核心标识符的值。

9. 发明申请

US20130238912A1 METHOD AND APPARATUS FOR MANAGING POWER IN A MULTI-CORE PROCESSOR 有权
标题翻译：用于在多核处理器中管理功率的方法和装置
公开(公告)号：US20130238912A1
公开(公告)日：2013-09-12
申请号：US13989280
申请日：2010-11-25
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
摘要翻译：提供了一种在具有两个或多个处理核心的多核数据处理系统中管理电力的方法，包括确定多核处理单元内的两个或多个处理核心的使用特性，并且取决于确定的使用特性，适应提供给两个或多个处理核心中的每一个的频率或电压，和/或调整提供给两个或多个处理核心中的每一个的启用信号。还提供了一种用于实施所公开的方法的装置。

10. 发明授权

US08255723B2 Device having multiple instruction execution modules and a management method 有权
标题翻译：具有多个指令执行模块和管理方法的设备
公开(公告)号：US08255723B2
公开(公告)日：2012-08-28
申请号：US12509285
申请日：2009-07-24
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/30189 , G06F9/3836 , G06F9/3869 , G06F9/3885 , Y02D10/171
摘要： A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.
摘要翻译：一种多指令执行模块装置，包括第一指令执行模块和第二指令执行模块以及上下文切换控制器; 其中所述第一指令执行模块在逻辑上与所述第二指令执行模块相同，但是与所述第二指令执行模块基本上不同于至少一个功耗特性; 其中所述上下文切换控制器控制所述第一指令执行模块和所述第二指令执行模块之间的上下文切换; 其中已经传送其上下文的指令执行模块被关闭。

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