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1. 发明申请

US20090207660A1 PROGRAM METHOD OF FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件的程序方法
公开(公告)号：US20090207660A1
公开(公告)日：2009-08-20
申请号：US12425025
申请日：2009-04-16
申请人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
发明人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.
摘要翻译：描述包括用于增加程序速度的MLC的闪速存储器件的擦除和编程方法。在擦除方法中，MLC被预编程，使得可以减少分布有MLC的阈值电压的电压范围。因此，当擦除MLC时，可以减少故障发生率，可以提高MLC的阈值电压分布，并且可以在随后的程序操作中缩短整个编程时间。

2. 发明申请

US20080230830A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080230830A1
公开(公告)日：2008-09-25
申请号：US12052914
申请日：2008-03-21
申请人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
发明人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
IPC分类号： H01L29/792 , H01L21/28 , H01L21/762
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

3. 发明授权

US07990771B2 Program method of flash memory device 有权
标题翻译：闪存设备的程序方法
公开(公告)号：US07990771B2
公开(公告)日：2011-08-02
申请号：US12425025
申请日：2009-04-16
申请人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
发明人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
IPC分类号： G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are pre-programmed based on whether their individual threshold voltages are included in a first voltage range. The selected MLCs are pre-programmed with a pre-program (first) voltage; and the remaining MLCs are prohibited from pre-programming; then the remaining MLCs connected to the selected word line are programmed by applying a program (second) voltage that gradually rises from the pre-program voltage at a ratio of a step voltage n for the selected line.
摘要翻译：一种擦除和编程包括多电平单元（MLC）的闪速存储器件的方法。选择字线的MLC，并且基于它们的各自的阈值电压是否被包括在第一电压范围中，一些MLC被预先编程。所选择的MLC以预编程（第一）电压进行预编程; 其余的MLC被禁止进行预编程; 那么连接到所选择的字线的剩余MLC通过应用从预编程电压以所选行的阶梯电压n的比率逐渐上升的程序（第二）电压被编程。

4. 发明授权

US07978532B2 Erase method of flash memory device 有权
标题翻译：闪存设备的擦除方法
公开(公告)号：US07978532B2
公开(公告)日：2011-07-12
申请号：US12424984
申请日：2009-04-16
申请人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
发明人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
IPC分类号： G11C16/06 , G11C16/14 , G11C16/10
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.
摘要翻译：包括用于增加程序速度的MLC的闪存设备的擦除和编程方法。在擦除方法中，MLC被预编程，使得可以减少分布有MLC的阈值电压的电压范围。因此，当擦除MLC时，可以减少故障发生率，可以提高MLC的阈值电压分布，并且可以在随后的程序操作中缩短整个编程时间。

5. 发明申请

US20110204430A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110204430A1
公开(公告)日：2011-08-25
申请号：US13097479
申请日：2011-04-29
申请人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
发明人： Se Jun KIM , Eun Seok CHOI , Kyoung Hwan PARK , Hyun Seung YOO , Myung Shik LEE , Young Ok HONG , Jung Ryul AHN , Yong Top KIM , Kyung Pil HWANG , Won Sic WOO , Jae Young PARK , Ki Hong LEE , Ki Seon PARK , Moon Sig JOO
IPC分类号： H01L29/792 , B82Y99/00
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

6. 发明授权

US07955960B2 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07955960B2
公开(公告)日：2011-06-07
申请号：US12052914
申请日：2008-03-21
申请人： Se Jun Kim , Eun Seok Choi , Kyoung Hwan Park , Hyun Seung Yoo , Myung Shik Lee , Young Ok Hong , Jung Ryul Ahn , Yong Top Kim , Kyung Pil Hwang , Won Sic Woo , Jae Young Park , Ki Hong Lee , Ki Seon Park , Moon Sig Joo
发明人： Se Jun Kim , Eun Seok Choi , Kyoung Hwan Park , Hyun Seung Yoo , Myung Shik Lee , Young Ok Hong , Jung Ryul Ahn , Yong Top Kim , Kyung Pil Hwang , Won Sic Woo , Jae Young Park , Ki Hong Lee , Ki Seon Park , Moon Sig Joo
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

7. 发明申请

US20090201728A1 Erase Method of Flash Memory Device 有权
标题翻译：闪存设备的擦除方法
公开(公告)号：US20090201728A1
公开(公告)日：2009-08-13
申请号：US12424984
申请日：2009-04-16
申请人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
发明人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
IPC分类号： G11C16/02 , G11C16/16 , G11C16/06
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.
摘要翻译：描述包括用于增加程序速度的MLC的闪速存储器件的擦除和编程方法。在擦除方法中，MLC被预编程，使得可以减少分布有MLC的阈值电压的电压范围。因此，当擦除MLC时，可以降低失败发生率，可以提高MLC的阈值电压分布，并且可以在随后的程序操作中缩短整个编程时间。

8. 发明授权

US07539057B2 Erase and program method of flash memory device for increasing program speed of flash memory device 有权
标题翻译：闪存设备的擦除和编程方法，用于提高闪存设备的程序速度
公开(公告)号：US07539057B2
公开(公告)日：2009-05-26
申请号：US11275279
申请日：2005-12-21
申请人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
发明人： Kyung Pil Hwang , Hyung Seok Kim , Keum Hwan Noh , Ju In Kim , Min Kyu Lee , Seok Jin Joo , Sook Kyung Kim
IPC分类号： G11C16/12 , G11C16/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.
摘要翻译：描述包括用于增加程序速度的MLC的闪速存储器件的擦除和编程方法。在擦除方法中，MLC被预编程，使得可以减少分布有MLC的阈值电压的电压范围。因此，当擦除MLC时，可以减少故障发生率，可以提高MLC的阈值电压分布，并且可以在随后的程序操作中缩短整个编程时间。

9. 发明授权

US06660604B1 Method of forming double junction region and method of forming transfer transistor using the same 有权
标题翻译：形成双结区域的方法和使用其形成转移晶体管的方法
公开(公告)号：US06660604B1
公开(公告)日：2003-12-09
申请号：US10314442
申请日：2002-12-09
申请人： Kyung Pil Hwang , Seoung Ouk Choi
发明人： Kyung Pil Hwang , Seoung Ouk Choi
IPC分类号： H01L21336
CPC分类号： H01L21/26513 , H01L21/28512 , H01L21/324 , H01L21/76802 , H01L27/115
摘要： The present invention relates to a method of forming a dual junction region and a method of forming a transfer transistor using the same. A low-concentration junction region is formed. A high-concentration junction region is formed at a portion of the low-concentration junction region by performing a high-concentration ion implantation process an ion implantation mask for an interlayer dielectric film in which a contact hole is formed so that the portion of the low-concentration junction region is exposed. With this structure, the distance between the high-concentration junction region and the well is sufficiently secured by controlling the distance between the high-concentration junction region and the well using the width of the contact hole formed in the interlayer dielectric film. Therefore, a stable characteristic can be secured upon application of a subsequent high voltage bias.
摘要翻译：本发明涉及形成双结区域的方法和使用其形成转移晶体管的方法。形成低浓度结区。通过对其中形成有接触孔的层间电介质膜的离子注入掩模进行高浓度离子注入处理，在低浓度结区的一部分处形成高浓度结区， - 浓度接合区域被暴露。利用这种结构，通过使用在层间电介质膜中形成的接触孔的宽度来控制高浓度接合区域和阱之间的距离，可以充分确保高浓度接合区域与阱之间的距离。因此，在施加随后的高电压偏压时可以确保稳定的特性。

10. 发明授权

US07715233B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07715233B2
公开(公告)日：2010-05-11
申请号：US12044441
申请日：2008-03-07
申请人： Kyung Pil Hwang , Won Sic Woo
发明人： Kyung Pil Hwang , Won Sic Woo
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08
摘要： A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon generated by the nose of the source line can be reduced. That is, at the time of a verifying operation performed during a program operation, the current concentrated on a common source line can be distributed and, therefore, the occurrence of under-programmed cells can be prevented.
摘要翻译：提供了一种非易失性存储器件。在一方面，非易失性存储器件包括两个或更多个公共源极线，其被包括在一个存储器单元块中，以便分配可能集中在一个公共源极线上的电流。结果，可以减少由源极线的鼻子产生的弹跳现象。也就是说，在编程操作期间执行的验证操作时，集中在公共源极线上的电流可以被分配，因此可以防止欠编程单元的发生。

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