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1. 发明授权

US07254075B2 Integrated circuit memory system having dynamic memory bank count and page size 有权
标题翻译：具有动态存储体积和页面大小的集成电路存储器系统
公开(公告)号：US07254075B2
公开(公告)日：2007-08-07
申请号：US10954941
申请日：2004-09-30
申请人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。在第二操作模式期间，第二多个数据从第一行存储单元传送到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器。在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

2. 发明授权

US07755968B2 Integrated circuit memory device having dynamic memory bank count and page size 有权
标题翻译：集成电路存储器件，具有动态存储体积计数和页面大小
公开(公告)号：US07755968B2
公开(公告)日：2010-07-13
申请号：US11834915
申请日：2007-08-07
申请人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.
摘要翻译：集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸第二种操作模式。存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

3. 发明申请

US20140003131A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20140003131A1
公开(公告)日：2014-01-02
申请号：US13860825
申请日：2013-04-11
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

4. 发明授权

US08595459B2 Micro-threaded memory 有权
标题翻译：微线程内存
公开(公告)号：US08595459B2
公开(公告)日：2013-11-26
申请号：US10998402
申请日：2004-11-29
申请人： Frederick A. Ware , Craig E. Hampel , Wayne S. Richardson , Chad A. Bellows , Lawrence Lai
发明人： Frederick A. Ware , Craig E. Hampel , Wayne S. Richardson , Chad A. Bellows , Lawrence Lai
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G09G5/399
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
摘要翻译：微线程存储器件。提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和最小访问时间间隔。

5. 发明申请

US20120170399A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20120170399A1
公开(公告)日：2012-07-05
申请号：US13410254
申请日：2012-03-01
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/10 , G11C8/00 , G11C8/18
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

6. 发明授权

US08154947B2 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US08154947B2
公开(公告)日：2012-04-10
申请号：US13239846
申请日：2011-09-22
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/14 , G06F5/76
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

7. 发明申请

US20090193202A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20090193202A1
公开(公告)日：2009-07-30
申请号：US12391873
申请日：2009-02-24
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G06F12/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

8. 发明授权

US08432766B2 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US08432766B2
公开(公告)日：2013-04-30
申请号：US13410254
申请日：2012-03-01
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/14
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

9. 发明申请

US20120020178A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20120020178A1
公开(公告)日：2012-01-26
申请号：US13239846
申请日：2011-09-22
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

10. 发明授权

US07505356B2 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US07505356B2
公开(公告)日：2009-03-17
申请号：US11853708
申请日：2007-09-11
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/14
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

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