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1. 发明授权

US6153493A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6153493A
公开(公告)日：2000-11-28
申请号：US116880
申请日：1998-07-16
申请人： Hiromi Makimoto , Moriyoshi Nakashima , Kojiro Yuzuriha , Makoto Ooi , Jun Sumino
发明人： Hiromi Makimoto , Moriyoshi Nakashima , Kojiro Yuzuriha , Makoto Ooi , Jun Sumino
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： A field oxide film which is fine and having smaller upheaval of a bird's head is formed, so as to improve electrical characteristic of a conductive layer formed with end portions positioned on the field oxide film. A planarizing silicon film is formed on a silicon nitride film and a thermal oxide film, so as to planarize a concave generated between the thermal oxide film and a silicon nitride film. The planarizing silicon film is thermally oxidized, so as to form a planarizing thermal oxide film integrated with the thermal oxide film. Thereafter, the planarizing thermal oxide film is etched back to form the field oxide film, and the silicon nitride film and a polycrystalline silicon film are removed. Thereafter, the conductive layer with end portions positioned on the field oxide film is formed.
摘要翻译：形成精细且具有较小的鸟头动作的场氧化膜，从而改善形成在位于场氧化膜上的端部的导电层的电特性。在氮化硅膜和热氧化膜上形成平坦化硅膜，以平坦化在热氧化膜和氮化硅膜之间产生的凹。平坦化硅膜被热氧化，以形成与热氧化膜一体化的平坦化热氧化膜。此后，平面化热氧化膜被回蚀以形成场氧化物膜，并且去除氮化硅膜和多晶硅膜。此后，形成具有位于场氧化膜上的端部的导电层。

2. 发明授权

US5572469A Static random access memory device having a single bit line configuration 失效
公开(公告)号：US5572469A
公开(公告)日：1996-11-05
申请号：US467632
申请日：1995-06-06
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

3. 发明授权

US5475638A Static random access memory device having a single bit line configuration 失效
标题翻译：具有单位线配置的静态随机存取存储器件
公开(公告)号：US5475638A
公开(公告)日：1995-12-12
申请号：US25470
申请日：1993-03-03
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.
摘要翻译：公开了具有单个位线配置的静态随机存取存储器（SRAM）。一个存储单元包括串联连接在数据存储电路1和单个位线BL之间的存取栅极晶体管Q5，Q6。在写入操作中，晶体管Q5，Q6的栅电极通过X字线升压电路7和Y字线升压电路8升压到超过电源电压的电平，以使数据存储电路处于不稳定的数据存储状态在由行地址信号和列地址信号选择的存储单元中。仅在期望的存储单元中执行数据写入，并且防止对其它存储单元的错误数据写入。

4. 发明授权

US06682985B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06682985B2
公开(公告)日：2004-01-27
申请号：US10040633
申请日：2002-01-09
申请人： Kojiro Yuzuriha , Naoki Tsuji
发明人： Kojiro Yuzuriha , Naoki Tsuji
IPC分类号： H01L2176
CPC分类号： H01L21/76235 , H01L21/31053 , H01L21/31055
摘要： A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained. The process is provided with the step of forming a multilayer film on a silicon substrate, the step of patterning the multilayer film and of etching the silicon substrate so as to create a trench, the step of forming an inner wall silicon oxide film on the inner wall surface of the trench, the step of forming a trench oxide layer so as to fill in the trench, the step of polishing the trench oxide layer through CMP polishing so as to expose the silicon nitride layer and the step of etching the trench oxide film, which has undergone the CMP polishing, by a thickness no more than the thickness of the inner wall silicon oxide film.
摘要翻译：可以获得半导体器件以及制造半导体器件的方法，其中形成宽的沟槽分离带而不会从硅衬底引出舀出。该工艺提供了在硅衬底上形成多层膜的步骤图案化多层膜和蚀刻硅衬底以形成沟槽的步骤，在沟槽的内壁表面上形成内壁氧化硅膜的步骤，形成沟槽氧化物层的步骤，以便填充沟槽，通过CMP抛光来研磨沟槽氧化物层以暴露氮化硅层和蚀刻已经经过CMP抛光的沟槽氧化膜的步骤，其厚度不大于厚度的内壁氧化硅膜。

5. 发明授权

US6069391A Semiconductor device with boosting circuit and detecting circuit 失效
标题翻译：具有升压电路和检测电路的半导体器件
公开(公告)号：US6069391A
公开(公告)日：2000-05-30
申请号：US933835
申请日：1997-09-19
申请人： Kojiro Yuzuriha
发明人： Kojiro Yuzuriha
IPC分类号： G11C16/06 , H01L21/761 , H01L21/8247 , H01L27/06 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L27/115 , H01L27/0629
摘要： A semiconductor device, including a circuit configuration formed on a semiconductor substrate, comprises: a boosting circuit for boosting an external power supply voltage to a plus voltage and a minus voltage; and a detecting circuit having a resistor formed of an impurity diffused layer so that the plus voltage and the minus voltage boosted by the boosting circuit are respectively connected to the resistor, to detect a potential at a prescribed point of said resistor so as to verify whether or not the boosting circuit has generated a desired potential.
摘要翻译：包括形成在半导体衬底上的电路结构的半导体器件包括：用于将外部电源电压升压到正电压和负电压的升压电路; 以及检测电路，其具有由杂质扩散层形成的电阻器，使得由升压电路升压的正电压和负电压分别连接到电阻器，以检测所述电阻器的规定点处的电位，以验证是否或者不是升压电路产生期望的电位。

6. 发明授权

US06551442B2 Method of producing semiconductor device and system for producing the same 失效
公开(公告)号：US06551442B2
公开(公告)日：2003-04-22
申请号：US09767132
申请日：2001-01-23
申请人： Kojiro Yuzuriha
发明人： Kojiro Yuzuriha
IPC分类号： H01L2100
CPC分类号： H01L21/76826 , H01L21/31111 , H01L21/316 , H01L21/6708 , H01L21/6715 , H01L21/67173 , H01L21/76825 , H01L21/76828 , Y10T29/41
摘要： A method of producing a semiconductor device having a multilayered wiring conductors and a system for producing the same. The nonuniformity of SOG coating film effectively suppressed and various treatments are simple and less time-consuming. A wiring conductor is formed on a semiconductor substrate, and an insulating layer covering the wiring conductor and the semiconductor substrate is formed, and the insulating layer is then subjected to a wet etching prior to the formation of SOG layer, thereby to increase a wettabiltity by the coating solution on the insulating layer.

7. 发明授权

US06011293A Semiconductor device having a structure for detecting a boosted potential 失效
标题翻译：具有用于检测升压电位的结构的半导体器件
公开(公告)号：US06011293A
公开(公告)日：2000-01-04
申请号：US64835
申请日：1998-04-23
申请人： Kojiro Yuzuriha , Makoto Ooi , Shinichi Kobayashi
发明人： Kojiro Yuzuriha , Makoto Ooi , Shinichi Kobayashi
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11541
摘要： A p-type well and an n-type well surrounding the p-type well are formed in a p-type semiconductor substrate under a field insulating film. A polysilicon resistance film is formed on the field insulating film simultaneously with a floating gate formed in a memory cell region. A polycide conductive film is formed on a interlayer insulating film simultaneously with an auxiliary bit line formed in the memory cell region, and the polycide conductive film is connected to the resistance film by a contact formed in a via hole. A wiring line formed on an interlayer insulating film is connected to the polycide conductive film by a contact formed in a via hole penetrating the interlayer insulating film. The two via holes are formed at positions corresponding to regions in the p-type well. A negative voltage is applied to the wiring line, and the potential of a predetermined point on the resistance film is measured.
摘要翻译：围绕p型阱的p型阱和n型阱在场绝缘膜下形成在p型半导体衬底中。与形成在存储单元区域中的浮动栅极同时在场绝缘膜上形成多晶硅电阻膜。在形成在存储单元区域中的辅助位线同时在层间绝缘膜上形成多晶硅导电膜，并且多孔体导电膜通过形成在通孔中的触点连接到电阻膜。形成在层间绝缘膜上的布线通过形成在穿过层间绝缘膜的通路孔中的接触而与多晶硅导电膜连接。两个通孔形成在对应于p型阱中的区域的位置处。对布线施加负电压，测定电阻膜上的规定点的电位。

8. 发明授权

US06841487B2 Method of manufacturing semiconductor device and flash memory 有权
标题翻译：制造半导体器件和闪存的方法
公开(公告)号：US06841487B2
公开(公告)日：2005-01-11
申请号：US10235661
申请日：2002-09-06
申请人： Kojiro Yuzuriha , Shu Shimizu , Tamotsu Tanaka , Takashi Yano
发明人： Kojiro Yuzuriha , Shu Shimizu , Tamotsu Tanaka , Takashi Yano
IPC分类号： H01L21/8244 , H01L21/8247 , H01L27/105 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/461
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11 , H01L27/1112 , H01L27/1116 , H01L27/11536 , H01L27/11546
摘要： A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.
摘要翻译：主要考虑半导体制造方法，改进以防止当使用单个图案化的抗蚀剂连续提供干法蚀刻和湿法蚀刻时抗蚀剂的改变的表面层被去除。在半导体基板上依次形成绝缘膜和导电层。在导电层上形成图案化的抗蚀剂。使用图案化的抗蚀剂作为掩模，干式蚀刻导电层。图案化抗蚀剂的表面层被部分去除。用图案化的抗蚀剂作为掩模，绝缘膜被湿蚀刻。

9. 发明授权

US06723641B2 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF DETERMINING FILM FORMATION TIME, CHAMBER, CHEMICAL VAPOR DEPOSITION APPARATUS AND BOAT THEREOF, ETCHING APPARATUS, AND FILM FORMATION PROCESS SYSTEM 有权
标题翻译：制造半导体器件的方法和确定膜形成时间的方法，室，化学气相沉积装置及其制造方法，蚀刻装置和膜形成过程系统
公开(公告)号：US06723641B2
公开(公告)日：2004-04-20
申请号：US10159999
申请日：2002-06-04
申请人： Kojiro Yuzuriha
发明人： Kojiro Yuzuriha
IPC分类号： H01L2144
CPC分类号： H01L21/67757 , C23C16/45557 , C23C16/56 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/02326 , H01L21/31612 , H01L21/67303 , H01L21/76224 , H01L21/76828 , H01L21/76831 , H01L21/76834 , H01L21/76897 , H01L27/10814 , H01L27/115 , H01L27/11521
摘要： After forming a phosphor-doped amorphous silicon film and before forming a bottom silicon oxide film, a heat treatment is performed while exhausting a gas from the vicinity of the silicon substrate. The heat treatment is performed at a temperature equal to or higher than that for forming the bottom silicon oxide film and at a pressure equal to or lower than that for forming the bottom silicon oxide film. Alternatively, after forming the phosphor-doped amorphous silicon film and before forming the bottom silicon oxide film, a TEOS oxide film and a phosphor-doped amorphous silicon film deposited on the back surface of the silicon substrate are removed. Further alternatively, these films deposited on the back surface of the silicon substrate are covered with a film which prevents gas desorption under the film formation condition for the bottom silicon oxide film.
摘要翻译：在形成磷光体掺杂非晶硅膜之后，在形成底部氧化硅膜之前，在从硅衬底附近排出气体的同时进行热处理。在等于或高于形成底部氧化硅膜的温度下进行热处理，并且其压力等于或低于形成底部氧化硅膜的压力。或者，在形成掺杂磷的非晶硅膜之后，在形成底部氧化硅膜之前，去除沉积在硅衬底背面上的TEOS氧化物膜和掺杂磷的非晶硅膜。或者，沉积在硅衬底的背面上的这些膜被膜覆盖，该膜在底部氧化硅膜的成膜条件下防止气体解吸。

10. 发明授权

US06458655B1 Method of manufacturing semiconductor device and flash memory 失效
标题翻译：制造半导体器件和闪存的方法
公开(公告)号：US06458655B1
公开(公告)日：2002-10-01
申请号：US09588475
申请日：2000-06-07
申请人： Kojiro Yuzuriha , Shu Shimizu , Tamotsu Tanaka , Takashi Yano
发明人： Kojiro Yuzuriha , Shu Shimizu , Tamotsu Tanaka , Takashi Yano
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11 , H01L27/1112 , H01L27/1116 , H01L27/11536 , H01L27/11546
摘要： A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.
摘要翻译：主要考虑半导体制造方法，改进以防止当使用单个图案化的抗蚀剂连续提供干法蚀刻和湿法蚀刻时抗蚀剂的改变的表面层被去除。在半导体基板上依次形成绝缘膜和导电层。在导电层上形成图案化的抗蚀剂。使用图案化的抗蚀剂作为掩模，干式蚀刻导电层。图案化抗蚀剂的表面层被部分去除。用图案化的抗蚀剂作为掩模，绝缘膜被湿蚀刻。

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