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1. 发明授权

US09197342B2 Communication device, communication system and communication method 有权
标题翻译：通信设备，通信系统和通信方式
公开(公告)号：US09197342B2
公开(公告)日：2015-11-24
申请号：US13541496
申请日：2012-07-03
申请人： Nobuhiro Kawahara , Koichi Usami
发明人： Nobuhiro Kawahara , Koichi Usami
IPC分类号： H04J3/07 , H04J3/16
CPC分类号： H04J3/1652 , H04J3/07
摘要： A communication device includes an addition unit which outputs a result of adding a predetermined number to the number of data blocks of a first signal, a comparison unit which, on the basis of comparison of the addition result with the number of data blocks of a second signal outputs the addition result of subtracting the number of data blocks of the second signal from the addition result, as a selection result, a data insertion unit which, on the basis of comparison of the selection result with the number of data blocks of the first signal, inserts either of the first signal and adjustment data into the second signal, and a storage unit which stores the selection result, and outputs the selection result stored last time to the addition unit, as the predetermined number.
摘要翻译：通信装置包括：加法单元，其输出与第一信号的数据块的数量相加的预定数量的结果;比较单元，其基于相加结果与第二信号的数据块的数量的比较信号输出从相加结果中减去第二信号的数据块数量的相加结果作为选择结果;数据插入单元，基于选择结果与第一个数据块的数据块数量的比较，信号，将第一信号和调整数据中的任一个插入到第二信号中，以及存储单元，存储选择结果，并将最后存储的选择结果输出到加法单元，作为预定数。

2. 发明申请

US20130011135A1 Communication device, communication system and communication method 有权
公开(公告)号：US20130011135A1
公开(公告)日：2013-01-10
申请号：US13541496
申请日：2012-07-03
申请人： Nobuhiro KAWAHARA , Koichi USAMI
发明人： Nobuhiro KAWAHARA , Koichi USAMI
IPC分类号： H04J14/00
CPC分类号： H04J3/1652 , H04J3/07
摘要： A communication device includes an addition unit which outputs a result of adding a predetermined number to the number of data blocks of a first signal, a comparison unit which, on the basis of comparison of the addition result with the number of data blocks of a second signal outputs the addition result of subtracting the number of data blocks of the second signal from the addition result, as a selection result, a data insertion unit which, on the basis of comparison of the selection result with the number of data blocks of the first signal, inserts either of the first signal and adjustment data into the second signal, and a storage unit which stores the selection result, and outputs the selection result stored last time to the addition unit, as the predetermined number.

3. 发明申请

US20090259789A1 MULTI-PROCESSOR, DIRECT MEMORY ACCESS CONTROLLER, AND SERIAL DATA TRANSMITTING/RECEIVING APPARATUS 审中-公开
标题翻译：多处理器，直接存储器访问控制器和串行数据发送/接收装置
公开(公告)号：US20090259789A1
公开(公告)日：2009-10-15
申请号：US12064179
申请日：2006-08-21
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06F13/28 , G06F13/36 , G06F3/00 , G06F13/362
CPC分类号： G06F13/28 , G06F13/362
摘要： A CPU 5 is provided with both the functionality of issuing an external bus access request directly to an external memory interface 3 and the functionality of issuing a DMA transfer request to a DMAC 4. Accordingly, in the case where data is randomly accessed at discrete addresses, an external bus access request is issued directly to the external memory interface 3, and in the case of data block transfer or page swapping as requested by a virtual memory management unit or the like, a DMA transfer request is issued to the DMAC 4, so that it is possible to effectively access the external memory 50.
摘要翻译： CPU 5具有直接向外部存储器接口3发出外部总线访问请求的功能和向DMAC 4发出DMA传送请求的功能。因此，在以离散地址随机访问数据的情况下直接向外部存储器接口3发出外部总线访问请求，并且在由虚拟存储器管理单元等请求的数据块传送或页面交换的情况下，向DMAC 4发出DMA传送请求，使得可以有效地访问外部存储器50。

4. 发明申请

US20090225084A1 DATA PROCESSING UNIT, DRAWING APPARATUS AND PIXEL PACKER 审中-公开
标题翻译：数据处理单元，绘图设备和像素包装机
公开(公告)号：US20090225084A1
公开(公告)日：2009-09-10
申请号：US12209872
申请日：2008-09-12
申请人： Shuhei KATO , Koichi Usami
发明人： Shuhei KATO , Koichi Usami
IPC分类号： G06T11/20 , G06F12/08 , G06F9/302
CPC分类号： G06T11/40 , G06F12/0875 , G06T1/60 , G09G5/001 , G09G5/393 , G09G2360/121
摘要： A data processing unit for performing a high speed drawing operation of arbitrary patterns even in individual pixels is provided. It is assumed that the color mode is set to 3 bits per pixel. A pixel “N” is written to a drawing position designated by a byte address [29:3] and a bit address [2:0]. The subsequent pixel “N+1” is written immediately after the pixel “N”. The next subsequent pixel “N+2” is written immediately after the pixel “N+1” to span the adjacent bytes. Thereby, the pixel data is continuously stored within each byte and across the boundary between bytes with no space. In this case, the operation of writing pixel data, i.e., the drawing is performed not in words or bytes but in pixels. In addition to this, high speed drawing is possible by the use of a caching system.
摘要翻译：提供了即使在各个像素中执行任意图案的高速绘图操作的数据处理单元。假设颜色模式被设置为每像素3位。像素“N”被写入由字节地址[29：3]指定的绘图位置和位地址[2：0]。随后的像素“N + 1”被立即写入像素“N”之后。紧接在像素“N + 1”之后写入下一个后续像素“N + 2”以跨越相邻字节。由此，像素数据被连续地存储在每个字节之间并跨越不具有空格的字节之间的边界。在这种情况下，写入像素数据（即，绘制）的操作不以字或字节执行，而是以像素执行。除此之外，通过使用缓存系统可以实现高速绘图。

5. 发明申请

US20080025346A1 Method and device for synchronizing and multiplexing asynchronous signals 审中-公开
标题翻译：用于同步和复用异步信号的方法和设备
公开(公告)号：US20080025346A1
公开(公告)日：2008-01-31
申请号：US11882002
申请日：2007-07-30
申请人： Tsugio Takahashi , Koichi Usami
发明人： Tsugio Takahashi , Koichi Usami
IPC分类号： H04J3/06
CPC分类号： H04J3/0623 , H04J3/0685 , H04J3/1611
摘要： A method and an apparatus for synchronizing and multiplexing asynchronous signals are presented that enable the plurality of asynchronous signals to be processed without increasing the scale of circuitry. Clock phase absorption sections allow respective asynchronous STM-N signals to switch to a system clock signal. In accordance with the system clock signal, a MSOH termination section, a pointer reception section and a memory section carry out MSOH termination processing, frame phase absorption processing and the like in serial on the asynchronous STM-N signals. Synchronous signals thus generated after frame phase absorption are multiplexed through processing of changing pointer values and the like by a pointer transmission section.
摘要翻译：提出了一种用于同步和复用异步信号的方法和装置，其能够在不增加电路规模的情况下处理多个异步信号。时钟相位吸收部分允许相应的异步STM-N信号切换到系统时钟信号。根据系统时钟信号，MSOH终端部分，指针接收部分和存储部分在异步STM-N信号上串行执行MSOH终止处理，帧相位吸收处理等。在帧相位吸收之后产生的同步信号通过指针传输部分改变指针值等进行复用。

6. 发明申请

US20090278845A1 IMAGE GENERATING DEVICE, TEXTURE MAPPING DEVICE, IMAGE PROCESSING DEVICE, AND TEXTURE STORING METHOD 审中-公开
标题翻译：图像产生装置，纹理映射装置，图像处理装置和纹理存储方法
公开(公告)号：US20090278845A1
公开(公告)日：2009-11-12
申请号：US12088935
申请日：2006-09-14
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06T17/00
CPC分类号： G06T15/005
摘要： A vertex sorter 114 converts a polygon structure instance into a polygon/sprite shared data Cl, and a vertex expander 116 converts a sprite structure instance into a polygon/sprite shared data Cl in the same format. Subsequent circuits 118, 120, 122, 124, 126, 11, 130 and 132 generate an image to be displayed in a screen on the basis of the polygon/sprite shared data Cl with the same format. It is possible to generate an image which is formed from any combination of polygons and sprites, while suppressing the hardware scale, and furthermore it is possible to increase the number of the polygons and sprites capable of simultaneously drawing without incurring an increased memory capacity.
摘要翻译：顶点分类器114将多边形结构实例转换为多边形/子画面共享数据C1，并且顶点扩展器116将子画面结构实例转换为相同格式的多边形/精灵共享数据C1。随后的电路118,120,122,124,126,11,130和132基于具有相同格式的多边形/子画面共享数据C1生成要在屏幕中显示的图像。可以在抑制硬件规模的同时产生由多边形和精灵的任意组合形成的图像，并且还可以增加能够同时绘制的多边形和子画面的数量，而不会增加存储容量。

7. 发明申请

US20090213110A1 IMAGE MIXING APPARATUS AND PIXEL MIXER 审中-公开
标题翻译：图像混合装置和像素混合器
公开(公告)号：US20090213110A1
公开(公告)日：2009-08-27
申请号：US11570982
申请日：2005-06-24
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06T1/00
CPC分类号： G09G5/395 , G09G5/001 , G09G2340/10 , G09G2340/12 , H04N1/387 , H04N5/265
摘要： An image mixing apparatus and a pixel mixer capable of mixing image data items having different pixel resolutions, and mixing image data items in an arbitrary display priority, irrespective of the order of mixing, even if the order of mixing is determined in advance is provided. Of two pixel data items having depth values “Zc” and “Zb”, one pixel data item having the depth value indicating that the pixel is located in a foreground position is selected by a pixel selection determination circuit 110. However, if a pixel data item has a hue indicating that the pixel is transparent, such a pixel data item is not selected but another pixel data item is selected instead. Multiplexers 112 to 116 output a pixel data item (hue “Hm”/color saturation “Sm”/brightness “Lm”) which is selected by the pixel selection determination circuit 110. Since pixel data items are input to the multiplexer 112 to 116 at different output rates, it is possible to mix images having different pixel resolutions.
摘要翻译：提供一种图像混合装置和能够混合具有不同像素分辨率的图像数据项的像素混合装置，并且即使预先确定混合顺序，也可以混合任意显示优先级的图像数据项，而与混合顺序无关。在具有深度值“Zc”和“Zb”的两个像素数据项中，通过像素选择确定电路110选择具有指示像素位于前景位置的深度值的一个像素数据项。然而，如果像素数据项目具有指示像素是透明的色调，这样的像素数据项目不被选择，而是选择另一个像素数据项目。复用器112至116输出由像素选择确定电路110选择的像素数据项（色调“Hm”/色彩饱和度“Sm”/亮度“Lm”）。由于像素数据项被输入到多路复用器112至116 不同的输出速率，可以混合具有不同像素分辨率的图像。

8. 发明申请

US20090157934A1 Data Processing Unit and Bus Arbitration Unit 失效
标题翻译：数据处理单位和总线仲裁股
公开(公告)号：US20090157934A1
公开(公告)日：2009-06-18
申请号：US11569753
申请日：2005-05-27
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06F13/14
CPC分类号： G06F13/364
摘要： An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.
摘要翻译：描述了一种有效的总线仲裁单元，其中可以尽可能地减少等待时间，直到总线主机获得总线所有权并提高总线的操作速率，同时提高数据传输的吞吐量。总线主机发出指示要读取或写入的数据大小的大小信号（例如，信号“CDSZ”）。状态机155向总线主机授予与大小信号相对应的总线周期的总线所有权，以便使总线主控器能够连续地读取或写入数据。对于与所要求的大小所请求的大小相对应的每一系列总线周期执行仲裁总线主人。由于由总线主机发出的尺寸信号作为指示数据传输所需和足够大小的尺寸信号，所以状态机155可以设置最佳的总线周期数。

9. 发明申请

US20080273030A1 DRAWING APPARATUS AND DRAWING METHOD 审中-公开
标题翻译：绘图装置和绘图方法
公开(公告)号：US20080273030A1
公开(公告)日：2008-11-06
申请号：US12108393
申请日：2008-04-23
申请人： SHUHEI KATO , Koichi Usami
发明人： SHUHEI KATO , Koichi Usami
IPC分类号： G06T17/00
CPC分类号： G06T11/40
摘要： A YSU (19) sorts structure instances #0 to #7 in order that the polygons #0 to #7 corresponding thereto are arranged in ascending order of the minimum Y-coordinates thereof. An RPU (9) sequentially reads the structure instances #0 to #7 sorted by the YSU (19), and performs the drawing process of corresponding polygons on the basis of the structure instances as read.
摘要翻译： YSU（19）对结构实例＃0〜＃7进行排序，使得与其对应的多边形＃0〜＃7以其最小Y坐标的升序排列。 RPU（9）依次读取由YSU（19）分类的结构实例＃0〜＃7，并根据读取的结构实例对相应的多边形进行绘制处理。

10. 发明授权

US07908416B2 Data processing unit and bus arbitration unit 失效
标题翻译：数据处理单元和总线仲裁单元
公开(公告)号：US07908416B2
公开(公告)日：2011-03-15
申请号：US11569753
申请日：2005-05-27
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00
CPC分类号： G06F13/364
摘要： An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.
摘要翻译：描述了一种有效的总线仲裁单元，其中可以尽可能地减少等待时间，直到总线主机获得总线所有权并提高总线的操作速率，同时提高数据传输的吞吐量。总线主机发出指示要读取或写入的数据大小的大小信号（例如，信号“CDSZ”）。状态机155向总线主机授予与大小信号相对应的总线周期的总线所有权，以使得总线主机能够连续地读取或写入数据。对于与总线主机所要求的大小相对应的每个系列总线，执行一次仲裁。由于由总线主机发出的尺寸信号作为指示数据传输所需和足够大小的尺寸信号，所以状态机155可以设置最佳的总线周期数。

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