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1. 发明申请

US20090259789A1 MULTI-PROCESSOR, DIRECT MEMORY ACCESS CONTROLLER, AND SERIAL DATA TRANSMITTING/RECEIVING APPARATUS 审中-公开
标题翻译：多处理器，直接存储器访问控制器和串行数据发送/接收装置
公开(公告)号：US20090259789A1
公开(公告)日：2009-10-15
申请号：US12064179
申请日：2006-08-21
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06F13/28 , G06F13/36 , G06F3/00 , G06F13/362
CPC分类号： G06F13/28 , G06F13/362
摘要： A CPU 5 is provided with both the functionality of issuing an external bus access request directly to an external memory interface 3 and the functionality of issuing a DMA transfer request to a DMAC 4. Accordingly, in the case where data is randomly accessed at discrete addresses, an external bus access request is issued directly to the external memory interface 3, and in the case of data block transfer or page swapping as requested by a virtual memory management unit or the like, a DMA transfer request is issued to the DMAC 4, so that it is possible to effectively access the external memory 50.
摘要翻译： CPU 5具有直接向外部存储器接口3发出外部总线访问请求的功能和向DMAC 4发出DMA传送请求的功能。因此，在以离散地址随机访问数据的情况下直接向外部存储器接口3发出外部总线访问请求，并且在由虚拟存储器管理单元等请求的数据块传送或页面交换的情况下，向DMAC 4发出DMA传送请求，使得可以有效地访问外部存储器50。

2. 发明申请

US20090278845A1 IMAGE GENERATING DEVICE, TEXTURE MAPPING DEVICE, IMAGE PROCESSING DEVICE, AND TEXTURE STORING METHOD 审中-公开
标题翻译：图像产生装置，纹理映射装置，图像处理装置和纹理存储方法
公开(公告)号：US20090278845A1
公开(公告)日：2009-11-12
申请号：US12088935
申请日：2006-09-14
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06T17/00
CPC分类号： G06T15/005
摘要： A vertex sorter 114 converts a polygon structure instance into a polygon/sprite shared data Cl, and a vertex expander 116 converts a sprite structure instance into a polygon/sprite shared data Cl in the same format. Subsequent circuits 118, 120, 122, 124, 126, 11, 130 and 132 generate an image to be displayed in a screen on the basis of the polygon/sprite shared data Cl with the same format. It is possible to generate an image which is formed from any combination of polygons and sprites, while suppressing the hardware scale, and furthermore it is possible to increase the number of the polygons and sprites capable of simultaneously drawing without incurring an increased memory capacity.
摘要翻译：顶点分类器114将多边形结构实例转换为多边形/子画面共享数据C1，并且顶点扩展器116将子画面结构实例转换为相同格式的多边形/精灵共享数据C1。随后的电路118,120,122,124,126,11,130和132基于具有相同格式的多边形/子画面共享数据C1生成要在屏幕中显示的图像。可以在抑制硬件规模的同时产生由多边形和精灵的任意组合形成的图像，并且还可以增加能够同时绘制的多边形和子画面的数量，而不会增加存储容量。

3. 发明申请

US20090213110A1 IMAGE MIXING APPARATUS AND PIXEL MIXER 审中-公开
标题翻译：图像混合装置和像素混合器
公开(公告)号：US20090213110A1
公开(公告)日：2009-08-27
申请号：US11570982
申请日：2005-06-24
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06T1/00
CPC分类号： G09G5/395 , G09G5/001 , G09G2340/10 , G09G2340/12 , H04N1/387 , H04N5/265
摘要： An image mixing apparatus and a pixel mixer capable of mixing image data items having different pixel resolutions, and mixing image data items in an arbitrary display priority, irrespective of the order of mixing, even if the order of mixing is determined in advance is provided. Of two pixel data items having depth values “Zc” and “Zb”, one pixel data item having the depth value indicating that the pixel is located in a foreground position is selected by a pixel selection determination circuit 110. However, if a pixel data item has a hue indicating that the pixel is transparent, such a pixel data item is not selected but another pixel data item is selected instead. Multiplexers 112 to 116 output a pixel data item (hue “Hm”/color saturation “Sm”/brightness “Lm”) which is selected by the pixel selection determination circuit 110. Since pixel data items are input to the multiplexer 112 to 116 at different output rates, it is possible to mix images having different pixel resolutions.
摘要翻译：提供一种图像混合装置和能够混合具有不同像素分辨率的图像数据项的像素混合装置，并且即使预先确定混合顺序，也可以混合任意显示优先级的图像数据项，而与混合顺序无关。在具有深度值“Zc”和“Zb”的两个像素数据项中，通过像素选择确定电路110选择具有指示像素位于前景位置的深度值的一个像素数据项。然而，如果像素数据项目具有指示像素是透明的色调，这样的像素数据项目不被选择，而是选择另一个像素数据项目。复用器112至116输出由像素选择确定电路110选择的像素数据项（色调“Hm”/色彩饱和度“Sm”/亮度“Lm”）。由于像素数据项被输入到多路复用器112至116 不同的输出速率，可以混合具有不同像素分辨率的图像。

4. 发明申请

US20090157934A1 Data Processing Unit and Bus Arbitration Unit 失效
标题翻译：数据处理单位和总线仲裁股
公开(公告)号：US20090157934A1
公开(公告)日：2009-06-18
申请号：US11569753
申请日：2005-05-27
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06F13/14
CPC分类号： G06F13/364
摘要： An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.
摘要翻译：描述了一种有效的总线仲裁单元，其中可以尽可能地减少等待时间，直到总线主机获得总线所有权并提高总线的操作速率，同时提高数据传输的吞吐量。总线主机发出指示要读取或写入的数据大小的大小信号（例如，信号“CDSZ”）。状态机155向总线主机授予与大小信号相对应的总线周期的总线所有权，以便使总线主控器能够连续地读取或写入数据。对于与所要求的大小所请求的大小相对应的每一系列总线周期执行仲裁总线主人。由于由总线主机发出的尺寸信号作为指示数据传输所需和足够大小的尺寸信号，所以状态机155可以设置最佳的总线周期数。

5. 发明授权

US07908416B2 Data processing unit and bus arbitration unit 失效
标题翻译：数据处理单元和总线仲裁单元
公开(公告)号：US07908416B2
公开(公告)日：2011-03-15
申请号：US11569753
申请日：2005-05-27
申请人： Shuhei Kato , Koichi Sano , Koichi Usami
发明人： Shuhei Kato , Koichi Sano , Koichi Usami
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00
CPC分类号： G06F13/364
摘要： An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.
摘要翻译：描述了一种有效的总线仲裁单元，其中可以尽可能地减少等待时间，直到总线主机获得总线所有权并提高总线的操作速率，同时提高数据传输的吞吐量。总线主机发出指示要读取或写入的数据大小的大小信号（例如，信号“CDSZ”）。状态机155向总线主机授予与大小信号相对应的总线周期的总线所有权，以使得总线主机能够连续地读取或写入数据。对于与总线主机所要求的大小相对应的每个系列总线，执行一次仲裁。由于由总线主机发出的尺寸信号作为指示数据传输所需和足够大小的尺寸信号，所以状态机155可以设置最佳的总线周期数。

6. 发明授权

US07561931B1 Sound processor 失效
标题翻译：声音处理器
公开(公告)号：US07561931B1
公开(公告)日：2009-07-14
申请号：US09636591
申请日：2000-08-10
申请人： Shuhei Kato , Koichi Sano
发明人： Shuhei Kato , Koichi Sano
IPC分类号： G06F17/00
CPC分类号： G10H7/006 , G06F3/16 , G10H1/46 , G10H7/06 , G10H2220/135 , G10H2250/541
摘要： A sound processor is formed on a single semiconductor device and has a function as a bus master for a common bus to positively and effectively access a resource on a common bus. Outputted is data over N sets (N being a natural number greater than 2) of sound channels through time division multiplexing to M sets (M being a natural number) of independent digital/analog converting means for converting sound-channel digital data into an analog sound signal. This reproduces pulse-code-modulated sound waveform data capable of simultaneously reproducing over a plurality of sets of sound channels represented by a product of M and N.
摘要翻译：在单个半导体器件上形成声音处理器，并且具有作为用于公共总线的总线主机的功能，以能够有效地访问公用总线上的资源。输出是通过时分复用到通过M组（M为自然数）的声音通道的N组（N为大于2的自然数）的数据，用于将声道数字数据转换为模拟声音信号。这再现了能够同时再现由M和N的乘积表示的多组声音通道的脉冲编码调制声音波形数据。

7. 发明授权

US6070205A High-speed processor system having bus arbitration mechanism 失效
标题翻译：具有总线仲裁机制的高速处理器系统
公开(公告)号：US6070205A
公开(公告)日：2000-05-30
申请号：US19277
申请日：1998-02-05
申请人： Shuhei Kato , Koichi Sano
发明人： Shuhei Kato , Koichi Sano
IPC分类号： G06F13/364 , G06F13/40 , G06F13/14 , G06F13/38
CPC分类号： G06F13/364
摘要： A high-speed processor system having a bus arbitration mechanism constructed on a single semiconductor chip. The processor system comprises at least one bus master, a plurality of buses and a plurality of bus slaves. Each bus comprises an independent address bus, an independent data bus and individual data transfer capability. Every bus master comprises a plurality of independent bus interfaces each connected to one of the buses. Each bus slave is connected to a bus that has corresponding data transfer capability. For a system having more than two bus masters, the system further comprises a plurality of bus arbitrators for arbitrating the access of each bus independently. The bus arbitrator receives a bus request signal from each bus master that requests the bus access and issues a bus grant signal to the bus master allowed to access the bus. The bus arbitrator comprises a plurality of priority order information storage devices for storing priority order information for all the bus masters connected to the bus. At every bus cycle, one set of priority order information is selected continuously and cyclically. When more than one bus master requests the bus access at the same time, the bus arbitrator determines which bus master may access the bus according to selected priority order information.
摘要翻译：具有构造在单个半导体芯片上的总线仲裁机制的高速处理器系统。处理器系统包括至少一个总线主机，多个总线和多个总线从机。每条总线包括独立的地址总线，独立的数据总线和独立的数据传输能力。每个总线主机包括多个独立的总线接口，每个连接到总线之一。每个总线从站连接到具有相应数据传输能力的总线。对于具有多于两个总线主机的系统，该系统还包括多个总线仲裁器，用于独立地仲裁每个总线的访问。总线仲裁器从每个总线主机接收到请求总线访问的总线请求信号，并向允许访问总线的总线主机发出总线授权信号。总线仲裁器包括多个优先级顺序信息存储装置，用于存储连接到总线的所有总线主机的优先顺序信息。在每个总线周期中，连续和周期性地选择一组优先级顺序信息。当多于一个总线主机同时请求总线访问时，总线仲裁器根据所选择的优先顺序信息确定哪个总线主机可以访问总线。

8. 发明授权

US07461394B1 Information processing apparatus connected to home TV set in use 失效
标题翻译：信息处理设备连接到家用电视机上使用
公开(公告)号：US07461394B1
公开(公告)日：2008-12-02
申请号：US09473963
申请日：1999-12-29
申请人： Koichi Sano , Shuhei Kato
发明人： Koichi Sano , Shuhei Kato
IPC分类号： H04N7/16 , G06F17/00 , G06F19/00 , A63F9/24 , A63F13/00
CPC分类号： A63F13/23 , A63F13/10 , A63F2300/1025 , A63F2300/209 , G06F9/4498 , G06F9/4881
摘要： An information processing apparatus includes man-machine interface, a semiconductor memory and an information processor. The semiconductor memory is configured by an application software contents portion, an application software engine, an operating system, an information processor hardware driver and a man-machine interface driver. Clear definition is given to interfaces between modules including software and hardware.
摘要翻译：信息处理装置包括人机接口，半导体存储器和信息处理器。半导体存储器由应用软件内容部分，应用软件引擎，操作系统，信息处理器硬件驱动器和人机界面驱动器构成。给出了包括软件和硬件在内的模块之间的接口的清晰定义。

9. 发明授权

US6043811A Color graphics processor 有权
公开(公告)号：US6043811A
公开(公告)日：2000-03-28
申请号：US344636
申请日：1999-06-25
申请人： Shuhei Kato , Koichi Sano
发明人： Shuhei Kato , Koichi Sano
IPC分类号： G09G5/02 , G09G5/22 , G09G5/30 , G09G5/42 , G09G5/36
CPC分类号： G09G5/02 , G09G5/30 , G09G5/42 , G09G5/024 , G09G5/222
摘要： A color graphic processor generating a picture screen formed by a two-dimensional pixel array for a raster-scan display. The color graphic processor comprises a scan image generator and a color video encoder. A circular pixel buffer having a plurality of pixel buffer units is used to buffer pixel data for drawing and displaying. The pixel buffer unit storing the pixel information of a current scanning position is circularly reused after the scanning position moves to the next one. The number of pixel buffer unit is flexible and does not have to be the same as the number of pixels in a horizontal scan line. A transparent information storage means and a transparent controller are included to reduce the size of the pixel buffer and control transparent pixels. The color video encoder processes digital luminosity, saturation and hue signals according to a video sync signal and a color burst flag signal to generate a digital luminosity signal and a digital chromaticity signal. The two video signals are combined to form a composite video signal. Digital-to-analog converter converts the digital video signals to analog video signals. The color video encoder supports both NTSC and PAL standard.

10. 发明授权

US6046751A Color graphics processor 失效
标题翻译：彩色图形处理器
公开(公告)号：US6046751A
公开(公告)日：2000-04-04
申请号：US19260
申请日：1998-02-05
申请人： Shuhei Kato , Koichi Sano
发明人： Shuhei Kato , Koichi Sano
IPC分类号： G09G5/02 , G09G5/22 , G09G5/30 , G09G5/42 , G06T1/00
CPC分类号： G09G5/02 , G09G5/30 , G09G5/42 , G09G5/024 , G09G5/222
摘要： A color graphic processor generating a picture screen formed by a two-dimensional pixel array for a raster-scan display. The color graphic processor comprises a scan image generator and a color video encoder. A circular pixel buffer having a plurality of pixel buffer units is used to buffer pixel data for drawing and displaying. The pixel buffer unit storing the pixel information of a current scanning position is circularly reused after the scanning position moves to the next one. The number of pixel buffer unit is flexible and does not have to be the same as the number of pixels in a horizontal scan line. A transparent information storage means and a transparent controller are included to reduce the size of the pixel buffer and control transparent pixels. The color video encoder processes digital luminosity, saturation and hue signals according to a video sync signal and a color burst flag signal to generate a digital luminosity signal and a digital chromaticity signal. The two video signals are combined to form a composite video signal. Digital-to-analog converter converts the digital video signals to analog video signals. The color video encoder supports both NTSC and PAL standard.
摘要翻译：产生由用于光栅扫描显示的二维像素阵列形成的图像屏幕的彩色图形处理器。彩色图形处理器包括扫描图像发生器和彩色视频编码器。使用具有多个像素缓冲单元的圆形像素缓冲器来缓冲用于绘制和显示的像素数据。存储当前扫描位置的像素信息的像素缓冲单元在扫描位置移动到下一个扫描位置之后被循环重复使用。像素缓冲单元的数量是灵活的，不必与水平扫描行中的像素数相同。包括透明信息存储装置和透明控制器以减小像素缓冲器的尺寸并控制透明像素。彩色视频编码器根据视频同步信号和色同步信号标志信号处理数字亮度，饱和度和色调信号，以产生数字亮度信号和数字色度信号。两个视频信号被组合以形成复合视频信号。数模转换器将数字视频信号转换为模拟视频信号。彩色视频编码器支持NTSC和PAL标准。

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