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1. 发明授权

US06542422B1 Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address 失效
标题翻译：半导体存储器件执行具有缺陷存储单元地址的高速一致比较操作
公开(公告)号：US06542422B1
公开(公告)日：2003-04-01
申请号：US10246455
申请日：2002-09-19
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo
IPC分类号： G11C700
CPC分类号： G11C29/842 , G11C7/1051 , G11C11/4087 , G11C2207/107
摘要： When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.
摘要翻译：当将输入的列地址CA和缺陷地址相互比较时，通过对缺陷地址进行逆转换而获得的预设缺陷地址和缺陷转换地址都被输入到比较电路。在比较电路中，在将地址转换应用于列地址CA之间进行切换时，并且当不对其进行地址转换时进行重合确定操作，从而可以在地址转换操作之后不使用列地址CA来实现一致比较; 因此，取消伴随转换操作的确定操作的延迟以执行高速数据读取。

2. 发明授权

US06781900B2 Semiconductor memory device with enhanced reliability 失效
标题翻译：具有增强可靠性的半导体存储器件
公开(公告)号：US06781900B2
公开(公告)日：2004-08-24
申请号：US10234256
申请日：2002-09-05
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
IPC分类号： G11C2900
CPC分类号： G11C29/027 , G11C29/02
摘要： The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.
摘要翻译：半导体存储器件具有作为工作模式的形式模式和测试模式。该程序电路包括熔丝元件，其中使用备用存储单元而不是有缺陷存储单元的地址被编程。程序电路确认在测试模式下比在正常模式下更严格的状态下的熔断器的断开状态。在测试模式和正常模式之间的结果不同的情况下，通过检测电路将异常通知给外部。在保险丝没有完全熔断的情况下，也可以在测试模式中检测这样的保险丝以排除有缺陷的芯片。

3. 发明授权

US5995435A Semiconductor memory device having controllable supplying capability of internal voltage 失效
标题翻译：具有可控的内部电压供应能力的半导体存储器件
公开(公告)号：US5995435A
公开(公告)日：1999-11-30
申请号：US137707
申请日：1998-08-21
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
摘要翻译：当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵当泵时钟和CBR模式信号被输入时。

4. 发明授权

US5986964A Semiconductor memory device consistently operating a plurality of memory cell arrays distributed in arrangement 失效
标题翻译：半导体存储器件一致地操作配置分布的多个存储单元阵列
公开(公告)号：US5986964A
公开(公告)日：1999-11-16
申请号：US184010
申请日：1998-11-02
申请人： Takuya Ariki , Takeshi Hamamoto , Kiyohiro Furutani
发明人： Takuya Ariki , Takeshi Hamamoto , Kiyohiro Furutani
IPC分类号： G11C7/22 , G11C8/12 , G11C11/406 , G11C7/00
CPC分类号： G11C8/12 , G11C11/406 , G11C7/22
摘要： A semiconductor memory device of the present invention is provided with a plurality of memory cell arrays distributed and thus arranged and having the same function, and a main control circuit and local control circuits that are structured hierarchically. Each memory cell array has its operation controlled directly by any of the local control circuits, wherein the main control circuit including a command producing circuit which responds to an externally applied signal to produce a control signal corresponding to a predetermined mode of operation, and a global control circuit which responds to a control command to generate a control signal for operating the entire semiconductor memory device consistently. The local control circuits receive the control signal from the global control circuit to cause memory cell arrays to perform a predetermined operation.
摘要翻译：本发明的半导体存储器件具有多个分布并由此布置并具有相同功能的存储单元阵列，以及分层构造的主控制电路和本地控制电路。每个存储单元阵列具有由任何本地控制电路直接控制的操作，其中主控制电路包括响应于外部施加的信号以产生对应于预定操作模式的控制信号的命令产生电路和全局控制电路响应于控制命令以一致地产生用于操作整个半导体存储器件的控制信号。本地控制电路从全局控制电路接收控制信号，以使存储单元阵列执行预定的操作。

5. 发明授权

US5699303A Semiconductor memory device having controllable supplying capability of internal voltage 失效
标题翻译：具有可控的内部电压供应能力的半导体存储器件
公开(公告)号：US5699303A
公开(公告)日：1997-12-16
申请号：US645347
申请日：1996-05-13
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
摘要翻译：当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵当泵时钟和CBR模式信号被输入时。

6. 发明授权

US06777920B2 Internal power-supply potential generating circuit 失效
标题翻译：内部电源电位发生电路
公开(公告)号：US06777920B2
公开(公告)日：2004-08-17
申请号：US10247337
申请日：2002-09-20
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Susumu Tanida
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Susumu Tanida
IPC分类号： G05F140
CPC分类号： G05F1/465
摘要： The internal power-supply potential generating circuit includes a reference potential generating circuit having small dependency on an external power-supply potential and on a temperature, an MOS transistor for pull up, a level shifter producing a potential lower than a reference potential by a prescribed voltage to a first node and producing a potential lower than an internal power-supply potential by a voltage of the sum of the prescribed potential and an offset potential to a second node, and a differential amplifier bringing an MOS transistor out of conduction in response to the potential of the second node reaching the potential of the first node. Thus, the reference potential may be set lower by the offset voltage, allowing stable reference potential and internal power-supply potential to be obtained even if the external power-supply potential is lowered.
摘要翻译：内部电源电位产生电路包括对外部电源电位和温度具有较小依赖性的参考电位产生电路，用于上拉的MOS晶体管，产生低于参考电位的电位的电平转换器电压到第一节点，并且通过对第二节点的预定电位和偏移电位之和的电压产生低于内部电源电位的电位;以及差分放大器，使得MOS晶体管响应于第二节点的潜力达到第一节点的潜力。因此，即使外部电源电位降低，也可以将偏置电压设定为较低的基准电位，能够获得稳定的基准电位和内部电源电位。

7. 发明授权

US06417715B2 Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit 失效
标题翻译：时钟产生电路产生与外部时钟相位差小变化的内部时钟，以及包括这种时钟发生电路的半导体存储器件
公开(公告)号：US06417715B2
公开(公告)日：2002-07-09
申请号：US09793999
申请日：2001-02-28
申请人： Takeshi Hamamoto , Kiyohiro Furutani
发明人： Takeshi Hamamoto , Kiyohiro Furutani
IPC分类号： G06F104
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0814 , H03L7/087 , H03L7/089 , H03L7/091
摘要： A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.
摘要翻译：时钟生成电路包括：时钟输入电路，接收互补的外部时钟以产生内部时钟;可变延迟电路，延迟内部时钟以产生内部操作时钟;复制电路进一步将内部操作时钟延迟预定时间，以产生返回时钟，直接比较外部时钟的电位电平与返回时钟的相位相交的相位比较器的相位比较器，以及根据相位比较器的相位比较结果来调整可变延迟电路的延迟量的延迟控制电路。

8. 发明授权

US06262931B1 Semiconductor memory device having voltage down convertor reducing current consumption 有权
标题翻译：具有降压转换器的半导体存储器件减少电流消耗
公开(公告)号：US06262931B1
公开(公告)日：2001-07-17
申请号：US09539893
申请日：2000-03-31
申请人： Takashi Kono , Kiyohiro Furutani , Takeshi Hamamoto , Katsuyoshi Mitsui
发明人： Takashi Kono , Kiyohiro Furutani , Takeshi Hamamoto , Katsuyoshi Mitsui
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C5/147
摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.
摘要翻译：控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。

9. 发明授权

US6091651A Semiconductor memory device with improved test efficiency 失效
标题翻译：半导体存储器件具有提高的测试效率
公开(公告)号：US6091651A
公开(公告)日：2000-07-18
申请号：US165502
申请日：1998-10-02
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Shigeru Kikuda
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Shigeru Kikuda
IPC分类号： G01R31/28 , G11C29/02 , G11C29/34 , G11C29/50 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/022 , G11C29/02 , G11C29/50
摘要： I/O lines in an I/O gate-sense amplifier portion are arranged in the order of IOA, /IOB, IOB, and /IOA. As a result, the potentials of adjacent I/O lines are necessarily different at the time of writing/reading the same data to/from a plurality of memory cells during a multi-bit test. Therefore, a short-circuit fault caused between adjacent I/O lines can be detected at the same time.
摘要翻译： I / O门检测放大器部分中的I / O线以IOA，/ IOB，IOB和/ IOA的顺序排列。结果，在多位测试期间，在从多个存储单元写入/读取相同数据时，相邻I / O线的电位必然是不同的。因此，可以同时检测相邻I / O线之间产生的短路故障。

10. 发明授权

US5841705A Semiconductor memory device having controllable supplying capability of internal voltage 失效
公开(公告)号：US5841705A
公开(公告)日：1998-11-24
申请号：US924501
申请日：1997-09-05
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.

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