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1. 发明授权

US09263304B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09263304B2
公开(公告)日：2016-02-16
申请号：US13186458
申请日：2011-07-19
申请人： Kenji Kanamitsu , Takuya Koga , Kazutoshi Anabuki
发明人： Kenji Kanamitsu , Takuya Koga , Kazutoshi Anabuki
IPC分类号： H01L21/30 , H01L21/67 , H01L21/02 , H01L21/311
CPC分类号： H01L21/67051 , B08B3/08 , B08B3/10 , H01L21/02057 , H01L21/31133 , H01L21/68764
摘要： Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step.A chemical solution discharged from a tip of a cleaning nozzle is brought into contact with protrusions of wafer chucks to thereby let static electricity of the chemical solution go to the wafer chucks, and subsequently, the cleaning nozzle is moved above the wafer to supply the chemical solution onto a top surface of the wafer, thereby suppressing abnormal discharge (damage) of the wafer due to charging of the chemical solution.
摘要翻译：抑制是由于在单晶片型晶片清洗工序中使用的清洗液的充电引起的半导体晶片的损坏。从清洗喷嘴的尖端排出的化学溶液与晶片卡盘的突起接触，由此使化学溶液的静电流进入晶片卡盘，随后将清洗喷嘴移动到晶片上方，以供给化学品溶液到晶片的顶面，从而抑制由于化学溶液的充电而导致的晶片的异常放电（损坏）。

2. 发明授权

US07524729B2 Method of manufacturing a semiconductor integrated circuit device having a trench 有权
标题翻译：具有沟槽的半导体集成电路器件的制造方法
公开(公告)号：US07524729B2
公开(公告)日：2009-04-28
申请号：US11189833
申请日：2005-07-27
申请人： Kenji Kanamitsu , Kouzou Watanabe , Norio Suzuki , Norio Ishitsuka
发明人： Kenji Kanamitsu , Kouzou Watanabe , Norio Suzuki , Norio Ishitsuka
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/823878 , H01L21/28061 , H01L21/76232 , H01L21/823481 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L29/4941 , H01L29/6659
摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
摘要翻译：一种半导体集成电路器件及其制造方法。由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。该倾斜面包含两个具有不同倾斜角的倾斜面。有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

3. 发明申请

US20080293230A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080293230A1
公开(公告)日：2008-11-27
申请号：US12183919
申请日：2008-07-31
申请人： Naohiro HOSODA , Kenji Kanamitsu
发明人： Naohiro HOSODA , Kenji Kanamitsu
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.
摘要翻译：在半导体器件中的最上层三层布线上布置富硅氧化物（SRO）膜。然后，对位于第三级布线上的氧化硅膜和氮化硅膜进行干蚀刻以暴露第三级布线的一部分，从而形成接合焊盘并在保险丝上形成开口。在该过程中，SRO膜用作蚀刻停止层。这优化了位于保险丝上的电介质膜的厚度。

4. 发明授权

US07303951B2 Method of manufacturing a trench isolation region in a semiconductor device 有权
标题翻译：在半导体器件中制造沟槽隔离区域的方法
公开(公告)号：US07303951B2
公开(公告)日：2007-12-04
申请号：US11028867
申请日：2005-01-05
申请人： Kenji Kanamitsu , Takashi Moriyama , Naohiro Hosoda
发明人： Kenji Kanamitsu , Takashi Moriyama , Naohiro Hosoda
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/823878
摘要： A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.
摘要翻译：一种制造半导体器件的方法，该半导体器件用于防止在形成元件隔离沟槽的步骤中在沟槽内部引起的针状突起的栅电极的电介质击穿，其中包括在氮化硅膜上形成氧化硅膜作为蚀刻掩模形成元件隔离沟槽，然后用氢氟酸蚀刻溶液清洗衬底的表面，以在通过使用提供的光致抗蚀剂膜作为掩模对图案化氮化硅膜的步骤之前提取沉积在氧化硅膜表面上的障碍物在其下面有防反射膜。

5. 发明授权

US06858515B2 Process for producing semiconductor device and semiconductor device produced thereby 失效
标题翻译：由此生产半导体器件和半导体器件的方法
公开(公告)号：US06858515B2
公开(公告)日：2005-02-22
申请号：US10638485
申请日：2003-08-12
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

6. 发明授权

US06635945B1 Semiconductor device having element isolation structure 失效
标题翻译：具有元件隔离结构的半导体器件
公开(公告)号：US06635945B1
公开(公告)日：2003-10-21
申请号：US09580953
申请日：2000-05-30
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L2900
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：描述半导体器件和形成器件的工艺。该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。

7. 发明申请

US20110237036A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20110237036A1
公开(公告)日：2011-09-29
申请号：US13155201
申请日：2011-06-07
申请人： Hiroyuki OHARA , Shino TAKAHASHI , Kenji KANAMITSU , Shuji MATSUO
发明人： Hiroyuki OHARA , Shino TAKAHASHI , Kenji KANAMITSU , Shuji MATSUO
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/32155 , H01L27/11 , H01L29/4933 , H01L29/665
摘要： By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 μm, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi2) layer is formed on an upper portion of the gate electrode by salicide technique.
摘要翻译：通过将惰性气体例如氮离子注入到从多晶硅膜的上表面到预定深度的nMIS形成区域中的多晶硅膜中，将多晶硅膜的上部转化为无定形形成非晶/多晶硅膜。然后，将n型杂质（例如磷）离子注入到非晶/多晶硅膜中以形成n型非晶/多晶硅膜，将n型非晶/多晶硅膜加工形成栅极长度短于0.1μm的栅电极，在栅电极的侧壁上形成由绝缘膜形成的侧壁，形成源极/漏极扩散层。此后，通过硅化物技术在栅电极的上部形成硅化钴（CoSi 2）层。

8. 发明申请

US20090029524A1 METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A TRENCH 审中-公开
标题翻译：制造具有TRENCH的半导体集成电路装置的方法
公开(公告)号：US20090029524A1
公开(公告)日：2009-01-29
申请号：US12244621
申请日：2008-10-02
申请人： Kenji KANAMITSU , Kouzou Watanabe , Norio Suzuki , Norio Ishitsuka
发明人： Kenji KANAMITSU , Kouzou Watanabe , Norio Suzuki , Norio Ishitsuka
IPC分类号： H01L21/762
CPC分类号： H01L21/823878 , H01L21/28061 , H01L21/76232 , H01L21/823481 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L29/4941 , H01L29/6659
摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
摘要翻译：一种半导体集成电路器件及其制造方法。由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。该倾斜面包含两个具有不同倾斜角的倾斜面。有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

9. 发明授权

US06544839B1 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06544839B1
公开(公告)日：2003-04-08
申请号：US09473297
申请日：1999-12-28
申请人： Kenji Kanamitsu , Kouzou Watanabe , Norio Suzuki , Norio Ishitsuka
发明人： Kenji Kanamitsu , Kouzou Watanabe , Norio Suzuki , Norio Ishitsuka
IPC分类号： H01L218242
CPC分类号： H01L21/823878 , H01L21/28061 , H01L21/76232 , H01L21/823481 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L29/4941 , H01L29/6659
摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
摘要翻译：一种半导体集成电路器件及其制造方法。由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。该倾斜面包含两个具有不同倾斜角的倾斜面。有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

10. 发明申请

US20100019324A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20100019324A1
公开(公告)日：2010-01-28
申请号：US12519489
申请日：2006-12-22
申请人： Hiroyuki Ohara , Shino Takahashi , Kenji Kanamitsu , Shuji Matsuo
发明人： Hiroyuki Ohara , Shino Takahashi , Kenji Kanamitsu , Shuji Matsuo
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/32155 , H01L27/11 , H01L29/4933 , H01L29/665
摘要： By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 μm, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi2) layer is formed on an upper portion of the gate electrode by salicide technique.
摘要翻译：通过将惰性气体例如氮离子注入到从多晶硅膜的上表面到预定深度的nMIS形成区域中的多晶硅膜中，将多晶硅膜的上部转化为无定形形成非晶/多晶硅膜。然后，将n型杂质（例如磷）离子注入到非晶/多晶硅膜中以形成n型非晶/多晶硅膜，将n型非晶/多晶硅膜加工形成栅极长度小于0.1μm的栅电极，在栅电极的侧壁上形成由绝缘膜形成的侧壁，形成源极/漏极扩散层。此后，通过硅化物技术在栅电极的上部形成硅化钴（CoSi 2）层。

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