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1. 发明授权

US06858515B2 Process for producing semiconductor device and semiconductor device produced thereby 失效
标题翻译：由此生产半导体器件和半导体器件的方法
公开(公告)号：US06858515B2
公开(公告)日：2005-02-22
申请号：US10638485
申请日：2003-08-12
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

2. 发明授权

US06635945B1 Semiconductor device having element isolation structure 失效
标题翻译：具有元件隔离结构的半导体器件
公开(公告)号：US06635945B1
公开(公告)日：2003-10-21
申请号：US09580953
申请日：2000-05-30
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L2900
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：描述半导体器件和形成器件的工艺。该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。

3. 发明申请

US20050196935A1 Semiconductor device and process for producing the same 有权
公开(公告)号：US20050196935A1
公开(公告)日：2005-09-08
申请号：US11108827
申请日：2005-04-19
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

4. 发明授权

US06881646B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06881646B2
公开(公告)日：2005-04-19
申请号：US10392916
申请日：2003-03-21
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生，从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。

5. 发明授权

US6090684A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6090684A
公开(公告)日：2000-07-18
申请号：US363184
申请日：1999-07-29
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
摘要翻译：浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。除去氧化物抑制膜和垫氧化膜的一部分以形成槽。特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。

6. 发明授权

US06562695B1 Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing 有权
标题翻译：半导体集成电路器件及其制造方法涉及使用圆形加工的浅槽隔离的缩小宽度
公开(公告)号：US06562695B1
公开(公告)日：2003-05-13
申请号：US09889018
申请日：2001-07-10
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要翻译：通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便具有凸形圆形的截面形状。

7. 发明授权

US06403446B1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06403446B1
公开(公告)日：2002-06-11
申请号：US09536447
申请日：2000-03-28
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S148/05
摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.
摘要翻译：制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力。

8. 发明授权

US07397104B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07397104B2
公开(公告)日：2008-07-08
申请号：US10778081
申请日：2004-02-17
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L21/00
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
摘要翻译：提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半。

9. 发明授权

US06720234B2 Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing 有权
标题翻译：半导体集成电路器件及其制造方法涉及使用圆形加工的浅槽隔离的缩小宽度
公开(公告)号：US06720234B2
公开(公告)日：2004-04-13
申请号：US10366423
申请日：2003-02-14
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要翻译：通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便具有凸形圆形的截面形状。

10. 发明授权

US07402473B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07402473B2
公开(公告)日：2008-07-22
申请号：US11108827
申请日：2005-04-19
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。通过减小半导体基板上的元件隔离槽的槽上缘周围的应力产生，从而优化元件隔离槽的形状并使器件更细，并提高器件电特性来制造器件。

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