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1. 再颁专利

USRE44190E1 Long instruction word controlling plural independent processor operations 有权
公开(公告)号：USRE44190E1
公开(公告)日：2013-04-30
申请号：US12580466
申请日：2009-10-16
申请人： Karl M. Guttag , Christopher Read , Keith Balmer
发明人： Karl M. Guttag , Christopher Read , Keith Balmer
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

2. 发明授权

US06185629B2 Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time 失效
标题翻译：数据传输控制器根据预定时间内的外部输入采用不同的存储器接口协议
公开(公告)号：US06185629B2
公开(公告)日：2001-02-06
申请号：US08208517
申请日：1994-03-08
申请人： Richard Simpson , Keith Balmer , Iain Robertson
发明人： Richard Simpson , Keith Balmer , Iain Robertson
IPC分类号： G06F1202
CPC分类号： G06F12/0215
摘要： This invention is a data processing apparatus which may interface with plural types of memories. A static decoder coupled to an external port decodes signals which from an external source that indicate the type of memory. Interface circuitry receives coded information from the static decoder and selects a protocol for information transfer. In the preferred embodiment, the protocol includes addressing information having multiplexed row/column addresses for accessing dynamic memories or un-multiplexed addresses for accessing static memories. The interface circuitry further includes a column address shifter. The column address shifter shifts address bits to vary the number of bits available for column addressing. The data processing apparatus attempts to use page mode addressing whenever possible. A lastpage register coupled to the address generator for stores previous address information. A comparator compares the previous address information stored in the lastpage register to the current address. If no page change is detected, the data processor supplies only the column address to the memory in a page mode cycle, or else the data processor supplies a full new address including both the row address and the column address. The data processing apparatus may also control the number of bits transferred. An external port supplies a bus size signal to a static decoder. The interface circuitry selects a a bus size protocol based upon the received bus size signal.
摘要翻译：本发明是可以与多种类型的存储器接口的数据处理装置。耦合到外部端口的静态解码器解码来自指示存储器类型的外部源的信号。接口电路从静态解码器接收编码信息，并选择信息传输协议。在优选实施例中，该协议包括具有用于访问动态存储器的复用行/列地址的寻址信息或用于访问静态存储器的未复用地址。接口电路还包括列地址移位器。列地址移位器移位地址位以改变列寻址可用的位数。数据处理设备尽可能尝试使用页面模式寻址。耦合到地址发生器的最后页寄存器用于存储先前的地址信息。比较器将存储在最后页寄存器中的先前地址信息与当前地址进行比较。如果没有检测到页面更改，则数据处理器在页面模式循环中仅向列表地址提供存储器，否则数据处理器将提供包含行地址和列地址的全新地址。数据处理装置还可以控制传送的比特数。外部端口向总线信号提供静态解码器。接口电路基于所接收的总线大小信号来选择总线大小协议。

3. 发明授权

US5974539A Three input arithmetic logic unit with shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带移位器和掩码发生器
公开(公告)号：US5974539A
公开(公告)日：1999-10-26
申请号：US160298
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30167 , G06F5/015
摘要： A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230）产生由功能信号选择的三个输入的组合。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位（235）的输出可以独立于算术逻辑单元（230）结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

4. 发明授权

US5742538A Long instruction word controlling plural independent processor operations 失效
公开(公告)号：US5742538A
公开(公告)日：1998-04-21
申请号：US632785
申请日：1996-04-15
申请人： Karl M. Guttag , Christopher J. Read , Keith Balmer
发明人： Karl M. Guttag , Christopher J. Read , Keith Balmer
IPC分类号： G06F7/52 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

5. 发明授权

US5724599A Message passing and blast interrupt from processor 失效
标题翻译：来自处理器的消息传递和爆炸中断
公开(公告)号：US5724599A
公开(公告)日：1998-03-03
申请号：US208171
申请日：1994-03-08
申请人： Keith Balmer , Karl M. Guttag , Robert J. Gove , Nicholas Ing-Simmons , Iain Robertson
发明人： Keith Balmer , Karl M. Guttag , Robert J. Gove , Nicholas Ing-Simmons , Iain Robertson
IPC分类号： G06F15/00 , G06F15/16
CPC分类号： G06F15/16
摘要： The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors. Additional actions such as interrupts, halt and cache memory flush may be controlled via the command word. In the preferred embodiment, a single command word may be directed to plural data processors. In the preferred embodiment, the command word bus and each of the data processors are disposed on a single semiconductor chip.
摘要翻译：本发明涉及多处理器系统内的通信。多处理器系统包括命令字总线和多个数据处理器。每个数据处理器连接到命令字总线，并包括命令电路，解码器和复位控制电路。命令电路可以在命令字总线上生成包括用于复位数据处理器的至少一个复位命令字的命令字。解码器解码通过命令字总线接收的命令字，并且至少包括用于对复位命令字进行解码的复位命令解码器。复位控制电路在接收到复位命令字时将数据处理器复位为与初始施加电力相对应的状态。每个命令字电路产生指示其所针对的特定数据处理器的命令字。只有数据处理器的预定子集可以发送定向到其他数据处理器的复位命令字。可以通过命令字来控制诸如中断，停止和高速缓冲存储器刷新等附加动作。在优选实施例中，单个命令字可以被引导到多个数据处理器。在优选实施例中，命令字总线和每个数据处理器设置在单个半导体芯片上。

6. 发明授权

US5696959A Memory store from a selected one of a register pair conditional upon the state of a selected status bit 失效
标题翻译：存储器根据所选状态位的状态从寄存器对中选定的一个存储器存储
公开(公告)号：US5696959A
公开(公告)日：1997-12-09
申请号：US478129
申请日：1995-06-07
申请人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
发明人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
IPC分类号： G06T1/60 , G06F9/302 , G06F9/312 , G06F9/318 , G06F9/32 , G06F9/34 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30094 , G06F9/30167 , G06F9/30189 , G06F9/30192 , G06F9/34 , G06F9/3842
摘要： A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0". In a further embodiment the register pair conditional write instruction is conditional. The write operation aborts if the designated condition is true. In the preferred embodiment of this invention, the arithmetic logic unit (230), the status register (210), the data registers (200) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71) as a part of a multiprocessor formed in a single integrated circuit (100) used in image processing.
摘要翻译：存储器存储操作来自由算术逻辑单元条件选择的一对寄存器之一。如果选择的状态位具有第一状态并且将与第一寄存器相关联的第二寄存器中的数据存储到存储器中，则指令逻辑电路（250,660）控制寻址电路（120）将第一寄存器中的数据存储到存储器中，如果所选状态位响应于寄存器对条件存储指令具有第二状态。这些位可以指示算术逻辑单元（230）的负输出，进位信号，溢出或零输出。寄存器对条件存储指令指定用于控制条件存储的特定一个状态位。指令逻辑电路（250,660）将选择的状态位替换为寄存器编号的最低有效位。因此，如果状态位为“1”，则存储器来自第一寄存器，如果状态位为“0”，则来自第二寄存器。在另一实施例中，寄存器对条件写指令是有条件的。如果指定的条件为真，则写入操作中止。在本发明的优选实施例中，算术逻辑单元（230），状态寄存器（210），数据寄存器（200）和指令解码逻辑（250,660）被体现在至少一个数字图像/图形处理器（71）作为在图像处理中使用的单个集成电路（100）中形成的多处理器的一部分。

7. 发明授权

US5640578A Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section 失效
标题翻译：具有多个独立部分的算术逻辑单元和从每个部分存储结果指示符位的寄存器
公开(公告)号：US5640578A
公开(公告)日：1997-06-17
申请号：US158742
申请日：1993-11-30
申请人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
发明人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
IPC分类号： G06F3/153 , G06F7/575 , G06F9/302 , G06F9/318 , G06F9/32 , G06F12/08 , G06T1/00 , G06T1/20 , G06T11/00 , G09G5/39 , H04N1/387 , G06F7/38 , G06F7/50
CPC分类号： G06F7/575 , G06F9/30014 , G06F9/30036 , G06F9/30094 , G06F9/30189 , G06F9/30192 , G06F2207/382 , G06F2207/3828 , G06F7/49905
摘要： An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections. The status detector supplies carry outs from each elementary section (301, 302, 303, 304) not coupled to an adjacent elementary section (301, 302, 303, 304) to the flags register (211). Status signals stored in the flags register (211) influence the combination of inputs formed by the arithmetic logic unit (230) within corresponding sections. An expand circuit (238) expands selected bits of flags register (211) to form a third input to a three input arithmetic logic unit (230).
摘要翻译：算术逻辑单元（230）可以被划分为多个独立部分（301,302,303,340）。对应于存储在标志寄存器（211）中的每个部分的进位状态信号的位零，其优选地包括比算术逻辑单元（230）的最大部分数量多的位。新的状态信号可以覆盖先前的状态信号或旋转存储的比特并存储新的状态信号。状态寄存器（210）存储确定算术逻辑单元（230）的段数的大小指示符。状态检测器对于算术逻辑单元（230）的每个基本部分（301,302,303,304）具有零检测器（321,322,323,324）。当小于最大数量的部分时，这些零信号为“与”（331,332,341）。多路复用器将基本（311,312,313,314）的进位输出耦合到相邻基本部分（301,302,303,304）的进位，或者不依赖于所选择的部分数量。状态检测器从没有耦合到相邻基本部分（301,302,303,304）的每个基本部分（301,302,303,304）提供进位到标志寄存器（211）。存储在标志寄存器（211）中的状态信号影响由相应部分内的算术逻辑单元（230）形成的输入的组合。扩展电路（238）扩展标志寄存器（211）的所选位以形成三输入算术逻辑单元（230）的第三输入。

8. 发明授权

US5606520A Address generator with controllable modulo power of two addressing capability 失效
标题翻译：地址发生器具有两种寻址能力的可控模数功率
公开(公告)号：US5606520A
公开(公告)日：1997-02-25
申请号：US484540
申请日：1995-06-07
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F7/38 , G06F12/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A data processing address generator includes a plurality of address registers, a plurality of index address registers, a modulo register storing a plurality of carry break indicators and an arithmetic unit. The arithmetic unit adds or subtracts a selected address register and a selected index register. The arithmetic unit generates a normal carry between a particular bit and the next more significant bit if a corresponding carry break indicator stored in said modulo register has a first digital state. The arithmetic unit breaks any carry between the particular bit and the next more significant bit if the corresponding carry break indicator has a second digital state. The carry break may be dependent upon a modulo qualifier bit being in an enabling state. The modulo qualifier bit may be stored in one of a plurality of qualifier registers corresponding to the address registers.
摘要翻译：数据处理地址生成器包括多个地址寄存器，多个索引地址寄存器，存储多个进位断点指示符的模数寄存器和运算单元。算术单元增加或减少选定的地址寄存器和选定的索引寄存器。如果存储在所述模数寄存器中的对应进位断点指示符具有第一数字状态，则运算单元在特定位和下一更高有效位之间产生正常进位。如果相应的进位断点指示符具有第二数字状态，运算单元将特定位和下一个更高有效位之间的任何进位断开。进位中断可以取决于模数限定位位于使能状态。模数限定符位可以存储在与地址寄存器对应的多个限定符寄存器之一中。

9. 发明授权

US5471592A Multi-processor with crossbar link of processors and memories and method of operation 失效
标题翻译：具有处理器和存储器的交叉连接的多处理器和操作方法
公开(公告)号：US5471592A
公开(公告)日：1995-11-28
申请号：US263504
申请日：1994-06-21
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

10. 发明授权

US07039795B2 System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data 有权
标题翻译：用于使用两级复用架构来执行对数据的传递，重新排列和复制操作的组合的系统和方法
公开(公告)号：US07039795B2
公开(公告)日：2006-05-02
申请号：US10172221
申请日：2002-06-14
申请人： Keith Balmer , Karl M. Guttag , Amarjit Singh Bhandal
发明人： Keith Balmer , Karl M. Guttag , Amarjit Singh Bhandal
IPC分类号： G06F9/315
CPC分类号： G06F9/30032
摘要： A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.
摘要翻译：使用复用架构来处理数据的方法包括：对数据执行多个第一复用器操作中的所选择的一个，然后执行多个第二复用器操作中的所选择的一个。第一复用器操作包括通过操作和多个位重排操作。第二多路复用器操作包括将所选择的比特复制到输出中相应的连续比特块的通过操作和多个比特复制操作。然后产生分别反映由第一和第二多路复用器产生的输出的结果。

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