专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08445338B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08445338B2
公开(公告)日：2013-05-21
申请号：US13549540
申请日：2012-07-16
申请人： Keiichi Sekiguchi , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
发明人： Keiichi Sekiguchi , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
IPC分类号： H01L21/84
CPC分类号： H01L27/1214 , H01L27/1203 , H01L27/127 , H01L29/78624 , H01L29/78645 , H01L29/78675 , H01L29/78696 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.
摘要翻译：本发明提供了一种制造半导体器件的方法，通过该方法，提供了包括有源层，与有源层接触的栅极绝缘膜和与有源层重叠的栅极与其间的栅极绝缘膜的晶体管。在有源层和第二区域之间，与栅电极重叠的第一区域的一部分添加杂质，而通过从有源层向一个倾斜方向添加杂质，而在有源层中添加杂质 ; 并且第二区域相对于第一区域位于一个方向上。

2. 发明授权

US08166946B2 Diesel engine start-up assisting device 有权
标题翻译：柴油发动机起动辅助装置
公开(公告)号：US08166946B2
公开(公告)日：2012-05-01
申请号：US12690328
申请日：2010-01-20
申请人： Keiichi Sekiguchi , Shigeo Yoshizaki , Hideki Asuke
发明人： Keiichi Sekiguchi , Shigeo Yoshizaki , Hideki Asuke
IPC分类号： F02N11/08 , F02N11/10
CPC分类号： F02P19/02 , F02N19/02 , F02P19/023 , F02P19/027
摘要： A diesel engine start-up assisting device includes a plurality of first-and-second switching elements 11a to 11d between a common direct-current power source 1 and a plurality of electrical load 3a to 3d, a plurality of start-up assisting main parts 10a to 10d and an input-and-output unit 7. The diesel engine start-up assisting device is constructed so as to enable start-up of a diesel engine when power distribution is applied to at least one of the electrical loads 3a to 3d. In arrangement, the first-and-second switching elements 11a to 11d, the start-up assisting main parts 10a to 10d and the input-and-output unit 7 are integrated into one package having a lead frame. Defining the first-and-second switching element as a pair of switching elements, the first-and-second switching elements 11a to 11d are arranged in parallel with each other on the lead frame, and the lead frame has a notch part formed between two pairs of switching elements adjoined to each other.
摘要翻译：柴油发动机起动辅助装置包括在公共直流电源1和多个电负载3a至3d之间的多个第一和第二开关元件11a至11d，多个启动辅助主要部分 10a至10d以及输入和输出单元7.柴油发动机起动辅助装置被构造成使得当对至少一个电负载3a至3d施加配电时能够启动柴油发动机。在第一和第二开关元件11a至11d，启动辅助主体部10a至10d以及输入和输出单元7中，集成在具有引线框架的一个封装中。将第一和第二开关元件定义为一对开关元件，第一和第二开关元件11a至11d在引线框架上彼此平行地布置，并且引线框架具有形成在两个开关元件之间的切口部分成对的开关元件彼此相邻。

3. 发明授权

US07776681B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07776681B2
公开(公告)日：2010-08-17
申请号：US12581328
申请日：2009-10-19
申请人： Keiichi Sekiguchi
发明人： Keiichi Sekiguchi
IPC分类号： H01L21/8238
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1266 , H01L27/13
摘要： A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel TFT is to be formed; thus, a source region and a drain region are formed in a semiconductor film of the other one of the p-channel TFT and the n-channel TFT by adding first impurity ions using the second resist mask and the third resist mask. After that, the first resist mask, the second resist mask, and the third resist mask are removed, and a source region and a drain region are formed in a semiconductor film of the one of the p-channel TFT and the n-channel TFT by adding second impurity ions using a fourth resist mask.
摘要翻译：留下用于形成用于p沟道TFT的栅电极和用于n沟道TFT的栅电极的第一抗蚀剂掩模和第二抗蚀剂掩模，并且在第一区域之后形成第三抗蚀剂掩模，要形成p沟道TFT和n沟道TFT; 因此，通过使用第二抗蚀剂掩模和第三抗蚀剂掩模添加第一杂质离子，在p沟道TFT和n沟道TFT中的另一个的半导体膜中形成源极区和漏极区。之后，去除第一抗蚀剂掩模，第二抗蚀剂掩模和第三抗蚀剂掩模，并且在p沟道TFT和n沟道TFT之一的半导体膜中形成源极区和漏极区通过使用第四抗蚀剂掩模添加第二杂质离子。

4. 发明授权

US09820379B2 Circuit board and electronic device including same 有权
公开(公告)号：US09820379B2
公开(公告)日：2017-11-14
申请号：US14124227
申请日：2012-05-30
申请人： Kiyotaka Nakamura , Yoshio Ohashi , Yuuichi Abe , Eisuke Hirano , Kunihide Shikata , Keiichi Sekiguchi
发明人： Kiyotaka Nakamura , Yoshio Ohashi , Yuuichi Abe , Eisuke Hirano , Kunihide Shikata , Keiichi Sekiguchi
IPC分类号： H05K1/09 , H01L23/367 , H01L23/498 , H01L23/15 , H05K1/02 , H05K1/03 , H05K1/11 , H05K3/40
CPC分类号： H05K1/09 , H01L23/15 , H01L23/3677 , H01L23/49827 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H05K1/0206 , H05K1/0306 , H05K1/115 , H05K3/4061 , H05K2201/0266 , H05K2201/0326 , H05K2203/049 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： A circuit board and an electronic device having the circuit board that includes a ceramic sintered body, a through conductor and a metal wiring layer. The ceramic sintered body includes a through hole penetrating from a first main surface to a second main surface thereof. The through conductor is in the through hole and has first and second ends. The metal wiring layer covering the first end and electrically connected to the through conductor. The through conductor includes: a first portion having a hollow cylinder shape, in contact with an inner wall of the through hole and extending from the first end to the second end; and a second portion having a columnar shape and disposed inside the first portion. The second portion has an average grain size of the metal larger than that in the first portion.

5. 发明授权

US07705358B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07705358B2
公开(公告)日：2010-04-27
申请号：US11957270
申请日：2007-12-14
申请人： Satoru Okamoto , Keiichi Sekiguchi
发明人： Satoru Okamoto , Keiichi Sekiguchi
IPC分类号： H01L27/14
CPC分类号： H01L29/78621 , H01L27/1214 , H01L27/127 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L2029/7863
摘要： It is an object to improve operation characteristics and reliability of a semiconductor device. A semiconductor device which includes an island-shaped semiconductor film having a channel-formation region, a first low-concentration impurity region, a second low-concentration impurity region, and a high-concentration impurity region including a silicide layer; a gate insulating film; a first gate electrode overlapping with the channel-formation region and the first low-concentration impurity region with the gate insulating film interposed therebetween; a second gate electrode overlapping with the channel-formation region with the gate insulating film and the first gate electrode interposed therebetween; and a sidewall formed on side surfaces of the first gate electrode and the second gate electrode. In the semiconductor device, a thickness of the gate insulating film is smaller in a region over the second low-concentration impurity region than in a region over the first low-concentration impurity region.
摘要翻译：本发明的目的是提高半导体器件的操作特性和可靠性。一种半导体器件，包括具有沟道形成区域，第一低浓度杂质区域，第二低浓度杂质区域和包括硅化物层的高浓度杂质区域的岛状半导体膜; 栅极绝缘膜; 与所述沟道形成区域和所述第一低浓度杂质区域重叠的第一栅极电极，其间具有所述栅极绝缘膜; 与所述沟道形成区域重叠的栅极电极与所述栅极绝缘膜和所述第一栅极电极重叠; 以及形成在第一栅电极和第二栅电极的侧表面上的侧壁。在半导体器件中，栅极绝缘膜的厚度在第二低浓度杂质区域以上比在第一低浓度杂质区域以上的区域小。

6. 发明申请

US20100041190A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100041190A1
公开(公告)日：2010-02-18
申请号：US12581328
申请日：2009-10-19
申请人： Keiichi SEKIGUCHI
发明人： Keiichi SEKIGUCHI
IPC分类号： H01L21/8238
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1266 , H01L27/13
摘要： A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel TFT is to be formed; thus, a source region and a drain region are formed in a semiconductor film of the other one of the p-channel TFT and the n-channel TFT by adding first impurity ions using the second resist mask and the third resist mask. After that, the first resist mask, the second resist mask, and the third resist mask are removed, and a source region and a drain region are formed in a semiconductor film of the one of the p-channel TFT and the n-channel TFT by adding second impurity ions using a fourth resist mask.
摘要翻译：留下用于形成用于p沟道TFT的栅电极和用于n沟道TFT的栅电极的第一抗蚀剂掩模和第二抗蚀剂掩模，并且在第一区域之后形成第三抗蚀剂掩模，要形成p沟道TFT和n沟道TFT; 因此，通过使用第二抗蚀剂掩模和第三抗蚀剂掩模添加第一杂质离子，在p沟道TFT和n沟道TFT中的另一个的半导体膜中形成源极区和漏极区。之后，去除第一抗蚀剂掩模，第二抗蚀剂掩模和第三抗蚀剂掩模，并且在p沟道TFT和n沟道TFT之一的半导体膜中形成源极区和漏极区通过使用第四抗蚀剂掩模添加第二杂质离子。

7. 发明授权

US07638372B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07638372B2
公开(公告)日：2009-12-29
申请号：US11452288
申请日：2006-06-14
申请人： Keiichi Sekiguchi
发明人： Keiichi Sekiguchi
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1266 , H01L27/13
摘要： A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel TFT is to be formed; thus, a source region and a drain region are formed in a semiconductor film of the other one of the p-channel TFT and the n-channel TFT by adding first impurity ions using the second resist mask and the third resist mask. After that, the first resist mask, the second resist mask, and the third resist mask are removed, and a source region and a drain region are formed in a semiconductor film of the one of the p-channel TFT and the n-channel TFT by adding second impurity ions using a fourth resist mask.
摘要翻译：留下用于形成用于p沟道TFT的栅电极和用于n沟道TFT的栅电极的第一抗蚀剂掩模和第二抗蚀剂掩模，并且在第一区域之后形成第三抗蚀剂掩模，要形成p沟道TFT和n沟道TFT; 因此，通过使用第二抗蚀剂掩模和第三抗蚀剂掩模添加第一杂质离子，在p沟道TFT和n沟道TFT中的另一个的半导体膜中形成源极区和漏极区。之后，去除第一抗蚀剂掩模，第二抗蚀剂掩模和第三抗蚀剂掩模，并且在p沟道TFT和n沟道TFT之一的半导体膜中形成源极区和漏极区通过使用第四抗蚀剂掩模添加第二杂质离子。

8. 发明申请

US20080188050A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080188050A1
公开(公告)日：2008-08-07
申请号：US12059652
申请日：2008-03-31
申请人： Keiichi SEKIGUCHI , Junichi KOEZUKA , Yasuyuki ARAI , Shunpei YAMAZAKI
发明人： Keiichi SEKIGUCHI , Junichi KOEZUKA , Yasuyuki ARAI , Shunpei YAMAZAKI
IPC分类号： H01L21/336
CPC分类号： H01L27/1214 , H01L27/1203 , H01L27/127 , H01L29/78624 , H01L29/78645 , H01L29/78675 , H01L29/78696 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.
摘要翻译：本发明提供了一种制造半导体器件的方法，通过该方法，提供了包括有源层，与有源层接触的栅极绝缘膜和与有源层重叠的栅极与其间的栅极绝缘膜的晶体管。在有源层和第二区域之间，与栅电极重叠的第一区域的一部分添加杂质，而通过从有源层向一个倾斜方向添加杂质，而在有源层中添加杂质 ; 并且第二区域相对于第一区域位于一个方向上。

9. 发明授权

US07365361B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07365361B2
公开(公告)日：2008-04-29
申请号：US10890234
申请日：2004-07-14
申请人： Keiichi Sekiguchi , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
发明人： Keiichi Sekiguchi , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
IPC分类号： H01L29/76
CPC分类号： H01L27/1214 , H01L27/1203 , H01L27/127 , H01L29/78624 , H01L29/78645 , H01L29/78675 , H01L29/78696 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.
摘要翻译：本发明提供一种制造半导体器件的方法，通过该方法，提供了包括有源层，与有源层接触的栅极绝缘膜和与有源层重叠的栅极与其间的栅极绝缘膜的晶体管。在有源层和第二区域之间，与栅电极重叠的第一区域的一部分添加杂质，而通过从有源层向一个倾斜方向添加杂质，而在有源层中添加杂质 ; 并且第二区域相对于第一区域位于一个方向上。

10. 发明申请

US20070108533A1 Integrated Circuit Having a Multipurpose Resistor for Suppression of a Parasitic Transistor or Other Purposes 有权
标题翻译：具有用于抑制寄生晶体管或其他目的的多用途电阻器的集成电路
公开(公告)号：US20070108533A1
公开(公告)日：2007-05-17
申请号：US11558804
申请日：2006-11-10
申请人： Keiichi Sekiguchi , Kazuya Aizawa
发明人： Keiichi Sekiguchi , Kazuya Aizawa
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L29/0634 , H01L29/404 , H01L29/7817
摘要： A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.
摘要翻译：包含两个不同于设计的LDMOSFET的复合集成电路，随之产生一个寄生晶体管。复合集成电路中集成了多用途电阻器，以防止寄生晶体管意外导通。在复合集成电路到开关电源的启动电路的预期应用中，多用途电阻器用作用于限制开关模式电源的启动期间的冲击电流的启动电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式