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    • 2. 发明授权
    • Speaker driving device and audio output system
    • 扬声器驱动装置和音频输出系统
    • US07764797B2
    • 2010-07-27
    • US11255986
    • 2005-10-24
    • Makoto YamamotoKeiichi Fujii
    • Makoto YamamotoKeiichi Fujii
    • H04R29/00
    • H03F3/20H03G3/007H03G3/3026
    • The present invention detects whether the supply voltage applied to the power supply terminal (3) is used for the dynamic speaker or for the piezoelectric speaker by the power supply voltage detection circuit (10), switches the gain of the amplifier circuit (8) in accordance with the detection result by the gain switching circuit (11) so that the same output power is produced for the same input signal in the respective speaker driving, and amplifies the input signal from the input terminal (5) by the amplifier circuit (8) having the gain to drive a speaker (1) that is connected to the output terminals (6, 7).
    • 本发明通过电源电压检测电路(10)检测施加到电源端子(3)的电源电压是否用于动力扬声器或压电扬声器,将放大电路(8)的增益 根据增益切换电路(11)的检测结果,对各扬声器驱动中的相同的输入信号产生相同的输出功率,并通过放大电路(8)放大来自输入端(5)的输入信号 )具有驱动连接到输出端子(6,7)的扬声器(1)的增益。
    • 3. 发明授权
    • Charge pump circuit
    • 电荷泵电路
    • US07474161B2
    • 2009-01-06
    • US11484775
    • 2006-07-12
    • Satoshi AzuhataToshinobu NagasawaTetsushi ToyookaKeiichi Fujii
    • Satoshi AzuhataToshinobu NagasawaTetsushi ToyookaKeiichi Fujii
    • H03B1/00
    • H02M3/07H02M1/36
    • While a charge pump activation/deactivation control circuit is outputting a high level signal, MOS transistors for short-circuiting a flying capacitor are off, and the charge pump circuit operates normally. When the charge pump activation/deactivation control circuit outputs a low level signal, the MOS transistors for short-circuiting the flying capacitor are turned on, and the charge pump circuit is deactivated. Consequently, the voltages at the terminals of the flying capacitor are the same and the charge charged therein is discharged. Therefore, when the charge pump circuit is activated again, the initial amount of charge charged to the flying capacitor is zero. Consequently, no large current flows through an output capacitor in the first discharging cycle after the re-activation.
    • 当电荷泵激活/去激活控制电路输出高电平信号时,用于使飞溅电容器短路的MOS晶体管关闭,并且电荷泵电路正常工作。 当电荷泵激活/去激活控制电路输出低电平信号时,用于使飞跨电容器短路的MOS晶体管导通,并且电荷泵电路被去激活。 因此,飞跨电容器的端子处的电压相同,并且其中充入的电荷被放电。 因此,当再次激活电荷泵电路时,充电到飞行电容器的初始充电量为零。 因此,在重新激活之后,在第一放电周期中没有大电流流过输出电容器。
    • 4. 发明申请
    • Charge pump circuit
    • 电荷泵电路
    • US20070013448A1
    • 2007-01-18
    • US11484775
    • 2006-07-12
    • Satoshi AzuhataToshinobu NagasawaTetsushi ToyookaKeiichi Fujii
    • Satoshi AzuhataToshinobu NagasawaTetsushi ToyookaKeiichi Fujii
    • H03L7/00
    • H02M3/07H02M1/36
    • While a charge pump activation/deactivation control circuit is outputting a high level signal, MOS transistors for short-circuiting a flying capacitor are off, and the charge pump circuit operates normally. When the charge pump activation/deactivation control circuit outputs a low level signal, the MOS transistors for short-circuiting the flying capacitor are turned on, and the charge pump circuit is deactivated. Consequently, the voltages at the terminals of the flying capacitor are the same and the charge charged therein is discharged. Therefore, when the charge pump circuit is activated again, the initial amount of charge charged to the flying capacitor is zero. Consequently, no large current flows through an output capacitor in the first discharging cycle after the re-activation.
    • 当电荷泵激活/去激活控制电路输出高电平信号时,用于使飞溅电容器短路的MOS晶体管关闭,并且电荷泵电路正常工作。 当电荷泵激活/去激活控制电路输出低电平信号时,用于使飞跨电容器短路的MOS晶体管导通,并且电荷泵电路被去激活。 因此,飞跨电容器的端子处的电压相同,并且其中充入的电荷被放电。 因此,当再次激活电荷泵电路时,充电到飞行电容器的初始充电量为零。 因此,在重新激活之后,在第一放电周期中没有大电流流过输出电容器。
    • 6. 发明申请
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US20060072696A1
    • 2006-04-06
    • US11232683
    • 2005-09-22
    • Taku KobayashiKeiichi Fujii
    • Taku KobayashiKeiichi Fujii
    • H03D3/24
    • H02M3/07
    • A semiconductor integrated circuit includes a charge pump circuit that repeats charge and discharge of a capacitor based on a clock signal when an ON/OFF control voltage is ON; a first delay circuit that delays the ON/OFF control voltage; a switch that shorts an output of the charge pump circuit and a GND input terminal when the delayed ON/OFF control voltage is OFF and opens when the delayed ON/OFF control voltage is ON; a first circuit block that is driven by a power voltage which is supplied from a power source input terminal and the charge pump circuit; and a second circuit block that is driven by a power voltage which is supplied from the power source input terminal and the GND input terminal. The first and second circuit blocks are mounted on the same semiconductor integrated circuit chip.
    • 半导体集成电路包括电荷泵电路,其在ON / OFF控制电压为ON时基于时钟信号重复电容器的充电和放电; 延迟ON / OFF控制电压的第一延迟电路; 当延迟的ON / OFF控制电压为OFF时,断开电荷泵电路的输出和GND输入端子的开关,当延迟的ON / OFF控制电压为ON时,该开关断开; 由从电源输入端子和电荷泵电路供给的电源电压驱动的第一电路块; 以及由从电源输入端子和GND输入端子提供的电源电压驱动的第二电路块。 第一和第二电路块安装在相同的半导体集成电路芯片上。
    • 7. 发明授权
    • Analog signal level detecting apparatus
    • 模拟信号电平检测装置
    • US06891407B2
    • 2005-05-10
    • US10799668
    • 2004-03-15
    • Taku KobayashiKeiichi FujiiTakuma Ishida
    • Taku KobayashiKeiichi FujiiTakuma Ishida
    • H03K5/08H03K5/01H03M1/18H03K5/22
    • H03M1/18
    • A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.
    • 整流的模拟输入信号通过电压比较器与阈值电压进行比较,并且基于比较结果切换升/降计数器的计数方向,并且锁存电路保持上/下计数器的输出,然后是 模拟数字转换电路将锁存信号的输出转换成直流电压。 此外,在上/下计数器中设置有独立提供用于递增计数操作的时钟和用于递减计数操作的时钟的两个输入端子,以及用于确定上升的复位定时的定时脉冲发生电路 提供了锁存电路的递减计数电路和锁存定时。
    • 8. 发明申请
    • Audio signal amplifier and audio apparatus having the same
    • 音频信号放大器和音频设备具有相同的功能
    • US20050047615A1
    • 2005-03-03
    • US10923003
    • 2004-08-23
    • Akihiro KawamuraKeiichi FujiiJunko Hirose
    • Akihiro KawamuraKeiichi FujiiJunko Hirose
    • H03F3/181H03G3/00H03G3/30H04H5/00H03F3/38H03F21/00
    • H03G3/301H03G3/007
    • To provide an audio signal amplifier and an audio apparatus having the same that automatically set the output level to an optimum level depending on power supply voltage and so on. The audio signal amplifier of the present invention has an input terminal for receiving an audio signal from outside; a demodulating level control signal input terminal for receiving a demodulating level control signal; a variable-gain amplifying circuit for inputting a gain control signal and the audio signal and amplifying the audio signal at an amplifying factor in response to the gain control signal; a demodulating circuit for receiving the output signal of the variable-gain amplifying circuit and a demodulating signal feedback amount control signal and outputting a demodulating signal obtained by demodulating the output signal of the variable-gain amplifying circuit, the demodulating signal varying in level in response to the demodulating signal feedback amount control signal, as the gain control signal; a control circuit for adjusting demodulating level for outputting the demodulating signal feedback amount control signal generated in response to the demodulating level control signal; and a first output terminal for outputting the output signal of the variable-gain amplifying circuit.
    • 提供一种音频信号放大器和具有根据电源电压等将输出电平自动设定为最佳电平的音频装置。 本发明的音频信号放大器具有用于从外部接收音频信号的输入端子; 解调电平控制信号输入端,用于接收解调电平控制信号; 可变增益放大电路,用于输入增益控制信号和音频信号,并响应于增益控制信号以放大因子放大音频信号; 用于接收可变增益放大电路的输出信号的解调电路和解调信号反馈量控制信号,并输出通过解调可变增益放大电路的输出信号而得到的解调信号,响应中的电平变化的解调信号 与解调信号反馈量控制信号作为增益控制信号; 用于调整解调电平的控制电路,用于输出响应于解调电平控制信号产生的解调信号反馈量控制信号; 以及用于输出可变增益放大电路的输出信号的第一输出端子。