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1. 发明申请

US20070266356A1 IC Design Flow Enhancement With CMP Simulation 有权
标题翻译： IC设计流程增强与CMP模拟
公开(公告)号：US20070266356A1
公开(公告)日：2007-11-15
申请号：US11688654
申请日：2007-03-20
申请人： Gwan Sin Chang , Yi-Kan Cheng , Ivy Chiu , Ke-Ying Su
发明人： Gwan Sin Chang , Yi-Kan Cheng , Ivy Chiu , Ke-Ying Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5031 , G06F2217/12 , Y02P90/265
摘要： An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.
摘要翻译：集成电路（IC）设计方法包括提供IC设计布局数据; 基于IC设计布局模拟化学机械抛光（CMP）工艺到材料层，以产生各种几何参数; 根据CMP工艺仿真的各种几何参数提取电阻和电容; 并且基于所提取的电阻和电容来执行电路定时分析。

2. 发明授权

US08336002B2 IC design flow enhancement with CMP simulation 有权
标题翻译： IC设计流程增强与CMP模拟
公开(公告)号：US08336002B2
公开(公告)日：2012-12-18
申请号：US11688654
申请日：2007-03-20
申请人： Gwan Sin Chang , Yi-Kan Cheng , Ivy Chiu , Ke-Ying Su
发明人： Gwan Sin Chang , Yi-Kan Cheng , Ivy Chiu , Ke-Ying Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5031 , G06F2217/12 , Y02P90/265
摘要： An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.
摘要翻译：集成电路（IC）设计方法包括提供IC设计布局数据; 基于IC设计布局模拟化学机械抛光（CMP）工艺到材料层，以产生各种几何参数; 根据CMP工艺仿真的各种几何参数提取电阻和电容; 并且基于所提取的电阻和电容来执行电路定时分析。

3. 发明授权

US08907441B2 Methods for double-patterning-compliant standard cell design 有权
标题翻译：符合双重图案的标准电池设计方法
公开(公告)号：US08907441B2
公开(公告)日：2014-12-09
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L21/70 , H01L27/02 , H01L23/528 , H01L27/118
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

4. 发明申请

US20110119648A1 ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY 有权
标题翻译：双文件技术的路由系统和方法
公开(公告)号：US20110119648A1
公开(公告)日：2011-05-19
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

5. 发明申请

US20070266248A1 System and Method for Design-for-Manufacturability Data Encryption 有权
标题翻译：用于制造可制造性数据加密的系统和方法
公开(公告)号：US20070266248A1
公开(公告)日：2007-11-15
申请号：US11687384
申请日：2007-03-16
申请人： Yi-Kan Cheng , Gwan Sin Chang , Jill Liu , Hsiao-Shu Chiao
发明人： Yi-Kan Cheng , Gwan Sin Chang , Jill Liu , Hsiao-Shu Chiao
IPC分类号： H04L9/00
CPC分类号： H04L9/00 , G06F21/72 , H04L2209/12
摘要： An encryption and decryption interface for integrated circuit (IC) design with design-for-manufacturing (DFM). The interface includes a decryption module embedded in an IC design tool; an encrypted DFM data provided to an IC designer authorized for utilizing the encrypted DFM data; and a private key provided to the IC designer for decrypting the encrypted DFM data in the IC design tool.
摘要翻译：用于制造设计（DFM）的集成电路（IC）设计的加密和解密接口。该接口包括嵌入在IC设计工具中的解密模块; 提供给被授权使用加密的DFM数据的IC设计的加密的DFM数据; 以及提供给IC设计者的用于解密IC设计工具中加密的DFM数据的私钥。

6. 发明授权

US07801717B2 Method for smart dummy insertion to reduce run time and dummy count 有权
标题翻译：用于智能虚拟插入的方法，以减少运行时间和虚拟计数
公开(公告)号：US07801717B2
公开(公告)日：2010-09-21
申请号：US11625658
申请日：2007-01-22
申请人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
发明人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , H01L2924/0002 , H01L2924/00
摘要： A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
摘要翻译：一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

7. 发明申请

US20080176343A1 Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count 有权
标题翻译：用于智能虚拟插入的方法可减少运行时间和虚拟计数
公开(公告)号：US20080176343A1
公开(公告)日：2008-07-24
申请号：US11625658
申请日：2007-01-22
申请人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
发明人： Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
IPC分类号： H01L21/00
CPC分类号： G06F17/5072 , G06F17/5068 , H01L2924/0002 , H01L2924/00
摘要： A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
摘要翻译：一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

8. 发明申请

US20110193234A1 Methods for Double-Patterning-Compliant Standard Cell Design 有权
标题翻译：双图案化标准单元设计方法
公开(公告)号：US20110193234A1
公开(公告)日：2011-08-11
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

9. 发明授权

US08239806B2 Routing system and method for double patterning technology 有权
标题翻译：双重图案化技术的路由系统和方法
公开(公告)号：US08239806B2
公开(公告)日：2012-08-07
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

10. 发明授权

US08136168B2 System and method for design-for-manufacturability data encryption 有权
标题翻译：用于可制造性数据加密设计的系统和方法
公开(公告)号：US08136168B2
公开(公告)日：2012-03-13
申请号：US11687384
申请日：2007-03-16
申请人： Yi-Kan Cheng , Gwan Sin Chang , Jill Liu , Hsiao-Shu Chiao
发明人： Yi-Kan Cheng , Gwan Sin Chang , Jill Liu , Hsiao-Shu Chiao
IPC分类号： H04L29/06
CPC分类号： H04L9/00 , G06F21/72 , H04L2209/12
摘要： An encryption and decryption interface for integrated circuit (IC) design with design-for-manufacturing (DFM). The interface includes a decryption module embedded in an IC design tool; an encrypted DFM data provided to an IC designer authorized for utilizing the encrypted DFM data; and a private key provided to the IC designer for decrypting the encrypted DFM data in the IC design tool.
摘要翻译：用于制造设计（DFM）的集成电路（IC）设计的加密和解密接口。该接口包括嵌入在IC设计工具中的解密模块; 提供给被授权使用加密的DFM数据的IC设计的加密的DFM数据; 以及提供给IC设计者的用于解密IC设计工具中加密的DFM数据的私钥。

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