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    • 1. 发明授权
    • Tuner, digital demodulating apparatus, controlling method of the apparatus, computer program product for the apparatus, recording medium recording thereon the product, and digital receiver
    • 调谐器,数字解调装置,装置的控制方法,装置的计算机程序产品,在其上记录产品的记录介质和数字接收机
    • US07881672B2
    • 2011-02-01
    • US11654579
    • 2007-01-18
    • Nobuyoshi KaikiTakae SakaiMasayuki NatsumiKazumasa Kioi
    • Nobuyoshi KaikiTakae SakaiMasayuki NatsumiKazumasa Kioi
    • H04B17/00
    • H04L27/3863
    • A digital demodulating apparatus comprises a tuner constituted by circuit elements to perform channel select processing to a signal; a demodulator that performs demodulation processing to a signal output from the tuner; a power supply unit that supplies a normal power to each circuit element, and supplies to the circuit element a test power different from the normal power, over a first time period in place of the normal power; a test noise measuring unit that measures the intensity of test noise contained in a signal to be output from the tuner, when the power supply unit supplies the test power over the first time period; a comparing unit that compares the intensity of the test noise measured by the test noise measuring unit with a noise reference value as a reference for updating of the normal power; and a power updating unit that updates the intensity of the normal power on the basis of a result of the comparison by the comparing unit.
    • 数字解调装置包括由电路元件构成的调谐器,以对信号执行信道选择处理; 解调器,对从调谐器输出的信号进行解调处理; 电源单元,其向每个电路元件提供正常功率,并且在第一时间段内代替正常功率向电路元件提供不同于正常功率的测试功率; 测试噪声测量单元,当所述电源单元在所述第一时间段内提供测试功率时,测量从所述调谐器输出的信号中包含的测试噪声的强度; 比较单元,其将由所述测试噪声测量单元测量的测试噪声的强度与噪声参考值作为用于更新所述正常功率的参考值进行比较; 以及功率更新单元,其基于比较单元的比较结果来更新正常功率的强度。
    • 5. 发明授权
    • Sequential permutation apparatus for rearranging input data
    • 用于重新排列输入数据的顺序置换装置
    • US5956755A
    • 1999-09-21
    • US834463
    • 1997-04-11
    • Youji KanieKazumasa Kioi
    • Youji KanieKazumasa Kioi
    • G06F7/78G06F12/00G06F12/02H04N19/129H04N19/134H04N19/176H04N19/189H04N19/423H04N19/426H04N19/60G06F12/10
    • G06F7/785G06F12/0292
    • A switching circuit supplies a signal from a write memory selection terminal and its inverted signal to one of a first or a second selector and the other of the first or the second selector according to an output signal from a forward/backward translation selection terminal. In a forward translation process, the first and second selectors select a translated address on a translated address bus in a writing stage and select an input address on an input address bus in a reading stage. In a backward translation process, the selectors select the input address in the writing stage and select the translated address in the reading stage. Consequently, the forward translation and the backward translation are executed using the same translation table. An address translation table memory therefore stores therein only either a translation table for forward translation or a translation table for backward translation.
    • 开关电路根据来自前向/后向转换选择端子的输出信号,将来自写入存储器选择端的信号及其反相信号提供给第一或第二选择器中的一个,第一或第二选择器中的另一个。 在正向转换处理中,第一和第二选择器在写入阶段中选择翻译地址总线上的转换地址,并在读取阶段选择输入地址总线上的输入地址。 在向后翻译过程中,选择器在写入阶段选择输入地址,并在阅读阶段选择翻译的地址。 因此,使用相同的转换表执行向前平移和向后平移。 因此,地址转换表存储器仅存储用于正向转换的转换表或用于反向转换的转换表。
    • 6. 发明申请
    • OFDM DEMODULATOR, OFDM DEMODULATION METHOD, OFDM DEMODULATION PROGRAM, AND STORAGE MEDIUM
    • OFDM解调器,OFDM解调方法,OFDM解调程序和存储介质
    • US20100202552A1
    • 2010-08-12
    • US12599904
    • 2008-05-14
    • Atsushi SakaiArnaud SantraineAkira SaitoMasayuki NatsumiMamoru OkazakiKazumasa Kioi
    • Atsushi SakaiArnaud SantraineAkira SaitoMasayuki NatsumiMamoru OkazakiKazumasa Kioi
    • H04L1/02
    • H04L27/2662H04L5/0007H04L27/2605H04L27/2657H04L27/2676H04L27/2688
    • In a case where there are a plurality of spurious disturbing waves, each of which has a strong peak at a particular frequency, in a transmission band, correlation between the disturbing waves becomes nonconstant so that it becomes difficult to remove the correlation between the disturbing waves. An OFDM demodulator of the present invention includes a symbol integration circuit (131) for integrating a guard correlation signal in a symbol number direction, and an offset removal circuit (132) for removing an offset from the guard correlation signal integrated in the symbol number direction. An amplitude component due to the disturbing wave, which amplitude component is included in the guard correlation signal, is cancelled by the integration in the symbol number direction, so that it is possible to successfully remove the offset from the guard correlation signal. Therefore, it is possible to obtain symbol timing more precisely by use of a maximum value detecting circuit (124), and further, calculate a phase rotation amount more precisely by use of a phase finding circuit (125).
    • 在存在多个在特定频率具有强峰值的杂散干扰波的情况下,在传输频带中,干扰波之间的相关性变得不恒定,从而难以消除干扰波之间的相关性 。 本发明的OFDM解调器包括用于对符号数方向的保护相关信号进行积分的符号积分电路(131)和用于从符号数方向上积分的保护相关信号中去除偏移的偏移消除电路(132) 。 在保护相关信号中包含振幅分量的干扰波的振幅分量通过符号数方向的积分而消除,从而可以成功地从保护相关信号中去除偏移。 因此,可以通过使用最大值检测电路(124)更精确地获得符号定时,并且还通过使用相位求和电路(125)更精确地计算相位旋转量。
    • 8. 发明授权
    • MOS logic circuit with hold operation
    • MOS逻辑电路具有保持操作
    • US6009021A
    • 1999-12-28
    • US956541
    • 1997-10-23
    • Kazumasa Kioi
    • Kazumasa Kioi
    • H03K19/0185H01L27/092H03K19/00H03K19/0948H03K19/096G11C16/04
    • H03K19/0019H01L27/0928H03K19/0963
    • A MOS logic circuit is charged by adiabatic charging, and is composed of a clamp circuit having a pair of PMOS transistors, and two functional circuits, each having at least one NMOS transistor, a gate electrode of each of the NMOS transistors being an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal of each functional circuit being connected to a drain electrode of the corresponding PMOS transistor, thus forming an output node. A substrate electrode of each of the NMOS transistors making up the two functional circuits is cross-connected to the output node of the other functional circuit. In this way, even in the HOLD operation, in which both input nodes fall to low level, the NMOS transistor which is to output low level becomes depletion mode, and the outputting operations are stabilized without increasing circuit size.
    • MOS逻辑电路由绝热充电充电,由具有一对PMOS晶体管的钳位电路和两个功能电路组成,每个具有至少一个NMOS晶体管,每个NMOS晶体管的栅电极为输入节点 每个功能电路的一个端子连接到公共恒压电源,并且每个功能电路的另一个端子连接到相应PMOS晶体管的漏电极,从而形成输出节点。 构成两个功能电路的每个NMOS晶体管的基板电极交叉连接到另一个功能电路的输出节点。 以这种方式,即使在两个输入节点都变为低电平的HOLD操作中,要输出低电平的NMOS晶体管变成耗尽模式,并且在不增加电路尺寸的情况下稳定输出操作。