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    • 2. 发明授权
    • Image data storage/processing apparatus
    • 图像数据存储/处理装置
    • US5428389A
    • 1995-06-27
    • US104928
    • 1993-08-12
    • Kenji ItoKaoru AdachiOsamu Saito
    • Kenji ItoKaoru AdachiOsamu Saito
    • G11C7/10H04N1/21H04N7/30H04N5/76H04N9/64
    • H04N1/2137G11C7/1027H04N1/2112H04N1/2158H04N19/60
    • An image data storage/processing apparatus is provided, which is particularly applicable to an electronic still camera, for example. The image data storage apparatus uses a dynamic RAM as a frame memory for temporarily storing image data representative of a field of an image to be recorded. The frame memory includes at least first and second memories. In the apparatus, there is provided a control so that the image data corresponding to the adjacent two pixel lines on the field are continuously read out in such a manner that they are simultaneously read out from the first and second memories, and the image data corresponding to one of the two pixel lines are read out with delay by the time required for reading out of the image data corresponding to the other pixel line. The image signal processing apparatus is capable of performing processing for writing in and reading out of various types of image data with a single memory.
    • 提供了一种特别适用于电子静态照相机的图像数据存储/处理装置。 图像数据存储装置使用动态RAM作为帧存储器,用于临时存储表示要记录的图像的场的图像数据。 帧存储器至少包括第一和第二存储器。 在该装置中,提供了一种控制,使得对应于场上的相邻两个像素线的图像数据以从第一和第二存储器同时读出的方式连续地读出,并且图像数据对应 到两个像素线中的一个被延迟地读出对应于另一个像素线的图像数据所需的时间。 图像信号处理装置能够执行用单个存储器写入和读出各种图像数据的处理。
    • 10. 发明授权
    • IC memory card system having a common data and address bus
    • 具有公共数据和地址总线的IC存储卡系统
    • US5361228A
    • 1994-11-01
    • US54575
    • 1993-04-30
    • Kaoru AdachiKatsuya Makioka
    • Kaoru AdachiKatsuya Makioka
    • G06K19/073G11C5/06G11C16/10G11C7/00G11C8/00
    • G11C16/102G11C5/066
    • An IC memory card system has a host for processing data, and an IC memory card removably connected to the host and incorporating a data recording medium implemented by an electrically erasable programmable semiconductor memory. The host comprises a system controller for sending to the memory card an address/data signal for distinguishing an address and data by a logical bilevel state, a read/write signal for distinguishing reading of data and writing of data in the semiconductor memory by a logical bilevel state, and an erase signal for erasing data stored in the semiconductor memory by a logical bilevel state as control signals, and bus clock pulses each being synchronous to a particular address and particular data. The IC memory card comprises a control circuit responsive to the address/data signal, read/write signal, erase signal and bus clock pulses for distinguishing an address and data, distinguishing reading and writing, and determining whether or not to erase existing data, and then reading or writing data in the semiconductor memory or erasing the existing data.
    • IC存储卡系统具有用于处理数据的主机,以及可移除地连接到主机并且并入由电可擦除可编程半导体存储器实现的数据记录介质的IC存储卡。 主机包括系统控制器,用于向存储卡发送用于区分地址和数据的逻辑双电平状态的地址/数据信号,用于区分数据读取和半导体存储器中的数据写入的逻辑的读/写信号 二级状态,以及擦除信号,用于通过逻辑二级状态擦除存储在半导体存储器中的数据作为控制信号,以及每个与特定地址和特定数据同步的总线时钟脉冲。 IC存储卡包括响应于地址/数据信号,读/写信号,擦除信号和总线时钟脉冲的控制电路,用于区分地址和数据,区分读和写,以及确定是否擦除现有数据,以及 然后读取或写入半导体存储器中的数据或擦除现有数据。