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1. 发明授权

US08298893B2 Method for manufacturing semiconductor device having multi-layered contact 有权
标题翻译：具有多层接触的半导体器件的制造方法
公开(公告)号：US08298893B2
公开(公告)日：2012-10-30
申请号：US12981118
申请日：2010-12-29
申请人： Jung Nam Kim
发明人： Jung Nam Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10894 , H01L27/10876 , H01L27/10885 , H01L27/10897
摘要： A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines.
摘要翻译：公开了一种用于制造半导体器件的方法，其减小了周边区域和单元区域之间的阶梯差。在半导体器件中，周边区域的金属接触被构造成多层结构。在单元区域中形成位线和存储节点接触之前，在周边区域中形成接触和线，使得单元区域与外围区域之间的台阶差减小，导致寄生线间电容。

2. 发明申请

US20060084023A1 METHOD OF AND AUXILIARY CLEANER FOR USE IN CLEANING A DIFFUSION FURNACE OF SEMICONDUCTOR MANUFACTURING EQUIPMENT 有权
标题翻译：用于清洁半导体制造设备的扩散炉的方法和辅助清洁剂
公开(公告)号：US20060084023A1
公开(公告)日：2006-04-20
申请号：US11197346
申请日：2005-08-05
申请人： Jung-Nam Kim
发明人： Jung-Nam Kim
IPC分类号： F27B5/04
CPC分类号： F27B17/0025 , C23C16/4405 , C30B31/10
摘要： A diffusion furnace of semiconductor manufacturing equipment is cleaned efficiently with a cleaning gas (ClF3) by using an auxiliary cleaner. The auxiliary cleaner is inserted into an inner tube of the wafer diffusion furnace. The auxiliary cleaner has a cylindrical body that occupies a central region of the interior of the furnace but is spaced apart from an inner wall surface of the inner tube. Accordingly, the gas is confined to a peripheral region adjacent the inner wall surface. As a result, a relatively small amount of the cleaning gas is comsumed during the cleaning process.
摘要翻译：通过使用辅助清洁器，通过清洁气体（ClF 3 3）有效地清洁半导体制造设备的扩散炉。辅助清洁剂插入晶片扩散炉的内管中。辅助清洁器具有圆柱体，其占据炉内部的中心区域，但与内管的内壁表面间隔开。因此，气体被限制在与内壁面相邻的周边区域。结果，在清洁过程中消耗相对少量的清洁气体。

3. 发明授权

US08197275B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08197275B2
公开(公告)日：2012-06-12
申请号：US12843461
申请日：2010-07-26
申请人： Jung Nam Kim
发明人： Jung Nam Kim
IPC分类号： H01L21/00
CPC分类号： H01L29/4236 , H01L29/66621
摘要： A method for manufacturing a semiconductor device is provided. A semiconductor substrate is etched to form a trench, a gate electrode is buried in the trench, an etch-back process thereon is performed to form a buried gate, and an insulating layer is formed at the entire surface with the trench. Subsequently, an ion implantation process with respect to the entire surface with the insulting layer is carried out, the dose amount in ion-implanted in the insulating layer of an upper portion of the semiconductor substrate is more than that of a sidewall in the trench. Therefore, when an etch process is performed to form a contact during a subsequent procedure, the short between the buried gate and the contact may be prevented using a difference between an etch rate of the insulating layer.
摘要翻译：提供一种制造半导体器件的方法。蚀刻半导体衬底以形成沟槽，将栅极埋在沟槽中，执行其上的蚀刻处理以形成掩埋栅极，并且在整个表面上与沟槽形成绝缘层。随后，进行与绝缘层相对于整个表面的离子注入工艺，离子注入半导体衬底的上部绝缘层中的剂量大于沟槽中的侧壁的剂量。因此，当在随后的过程中执行蚀刻处理以形成接触时，可以使用绝缘层的蚀刻速率之间的差异来防止掩埋栅极和接触之间的短路。

4. 发明申请

US20070024305A1 Apparatuses for inspecting pogo pins of an electrical die sorting system and a method for performing the same 失效
标题翻译：用于检查电动分模系统的弹簧销的装置及其执行方法
公开(公告)号：US20070024305A1
公开(公告)日：2007-02-01
申请号：US11490120
申请日：2006-07-21
申请人： Jung-Nam Kim
发明人： Jung-Nam Kim
IPC分类号： G01R31/02
CPC分类号： G01R1/06794
摘要： Apparatuses for inspecting pogo pins of an electrical die sorting (EDS) system are provided and a method for performing the same are provided. Apparatuses for inspecting pogo pins that delivers electrical signals between a tester and a probe when dies on a substrate are electrically tested are also provided. The apparatuses may include a lower plate, an upper plate and/or a sensing unit. The lower plate may be positioned under a pogo block including the pogo pins. The lower plate may include a conductive layer electrically connected to lower end portions of the pogo pins. The upper plate may be positioned over the pogo block. The upper plate may include conductive plugs corresponding to upper portions of the pogo pins. The sensing unit, for generating signals, may be coupled to an electrical contact between the conductive plugs and the pogo pins.
摘要翻译：提供了用于检查电动分模（EDS）系统的弹簧销的装置，并且提供了用于执行其的方法。还提供了用于检查在衬底上模具时在测试仪和探针之间传递电信号的弹簧针的装置。这些装置可以包括下板，上板和/或感测单元。下板可以位于包括弹簧销的弹簧块的下方。下板可以包括电连接到弹簧销的下端部分的导电层。上板可以位于pogo块上方。上板可以包括与弹簧销的上部相对应的导电插塞。用于产生信号的感测单元可以耦合到导电插头和弹簧销之间的电接触。

5. 发明申请

US20130168632A1 RESISTANCE VARIABLE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电阻可变存储器件及其制造方法
公开(公告)号：US20130168632A1
公开(公告)日：2013-07-04
申请号：US13596807
申请日：2012-08-28
申请人： Ji-Won MOON , Moon-Sig JOO , Sung-Hoon LEE , Jung-Nam Kim
发明人： Ji-Won MOON , Moon-Sig JOO , Sung-Hoon LEE , Jung-Nam Kim
IPC分类号： H01L45/00 , H01L21/02 , B82Y10/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1641
摘要： A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer.
摘要翻译：电阻可变存储器件包括：第一电极; 第二电极; 介于所述第一电极和所述第二电极之间的电阻变化层; 和纳米颗粒，其设置在电阻变化层中并具有比电阻变化层低的介电常数。

6. 发明申请

US20100258858A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100258858A1
公开(公告)日：2010-10-14
申请号：US12493085
申请日：2009-06-26
申请人： Jung Nam Kim
发明人： Jung Nam Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： Provided are a structure for reducing a parasitic capacitance generated between a gate electrode and a bit line in a highly integrated semiconductor memory apparatus, and a fabrication method thereof. The method of fabricating a semiconductor device according to the invention comprises: providing a substrate including an active region and an isolation region; forming a recess over the active region and the isolation region; etching the active region and the isolating region under the recess to form a fin structure; forming a buried gate over the fin structure in a lower portion of the recess; and forming an insulating layer filling in an upper portion of the recess.
摘要翻译：提供了一种用于降低在高度集成的半导体存储装置中的栅电极和位线之间产生的寄生电容的结构及其制造方法。根据本发明的制造半导体器件的方法包括：提供包括有源区和隔离区的衬底; 在所述有源区和所述隔离区上形成凹陷; 蚀刻所述有源区和所述凹部下方的所述隔离区以形成翅片结构; 在所述凹部的下部形成在所述翅片结构上方的掩埋栅极; 以及形成填充在所述凹部的上部的绝缘层。

7. 发明申请

US20090035916A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING FIN GATE 审中-公开
标题翻译：制造具有金属栅的半导体器件的方法
公开(公告)号：US20090035916A1
公开(公告)日：2009-02-05
申请号：US12118779
申请日：2008-05-12
申请人： Jung Nam KIM
发明人： Jung Nam KIM
IPC分类号： H01L21/762 , H01L21/302
CPC分类号： H01L21/76232 , H01L21/31116 , H01L29/66795
摘要： When manufacturing a semiconductor device, an isolation layer is formed on a semiconductor substrate to define an active region that includes gate forming area. Portions of the isolation layer that are adjacent to the gate forming area of the active region are etching by a dry cleaning process which utilizes NH3 gas and HF gas to form a fin pattern, in which the gate forming area of the active region protrude. Gate is formed on the fin pattern and on the etched portions of the isolation layer to surround the fin pattern. The dry cleaning process has a high etch selectivity between the semiconductor substrate and the isolation layer, which allows for the effective adjustment of the height of the fin patterns.
摘要翻译：当制造半导体器件时，在半导体衬底上形成隔离层以限定包括栅极形成区域的有源区。通过利用NH 3气体和HF气体形成其中有源区域的栅极形成区域突出的鳍状图案的干式清洗工艺来蚀刻与有源区域的栅极形成区域相邻的隔离层的部分。栅极形成在鳍状图案和隔离层的蚀刻部分上以包围鳍状图案。干法处理在半导体衬底和隔离层之间具有高蚀刻选择性，这允许有效调节鳍片图案的高度。

8. 发明授权

US07218097B2 Wafer test equipment and method of aligning test equipment 失效
标题翻译：晶圆试验设备和对准试验设备的方法
公开(公告)号：US07218097B2
公开(公告)日：2007-05-15
申请号：US11104337
申请日：2005-04-12
申请人： Jung-Nam Kim , Young-Jong Kim
发明人： Jung-Nam Kim , Young-Jong Kim
IPC分类号： G01R31/02
CPC分类号： G01R31/2891
摘要： Wafer test equipment includes a probe station having a wafer chuck for supporting a wafer, a test head disposed on the probe station, a manipulator for moving the test head to and from an upper surface of the probe station, and an alignment monitoring member for monitoring an alignment of the test head docked to the probe station.
摘要翻译：晶片测试设备包括具有用于支撑晶片的晶片卡盘的探针台，设置在探测台上的测试头，用于将测试头移动到探测台的上表面和从探测台的上表面移动的操纵器，以及用于监测的对准监视构件测试头对准到探测台的对准。

9. 发明授权

US07151386B2 Apparatus for testing integrated circuit chips 有权
标题翻译：集成电路芯片测试装置
公开(公告)号：US07151386B2
公开(公告)日：2006-12-19
申请号：US10832285
申请日：2004-04-27
申请人： Jung-Nam Kim
发明人： Jung-Nam Kim
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2886 , G01R3/00
摘要： A test apparatus, for testing electric properties of an integrated circuit, may include: a housing; a chuck on which an integrated circuit is placed as an object of the testing, the chuck being disposed in the housing; a tester part, having a probe needle, to test electric properties of the object, the tester part being attached to the housing; and a cleaning part to clean the probe needle, the cleaning part being disposed in the housing, and the cleaning part including a supporter, a mounting stand removably/attachably coupled to the supporter, and a polishing pad attached to the mounting stand to polish the probe needle.
摘要翻译：用于测试集成电路的电性能的测试装置可以包括：壳体; 作为测试对象放置集成电路的卡盘，卡盘设置在壳体中; 测试器部件，具有探针，用于测试所述物体的电特性，所述测试器部件附接到所述壳体; 以及用于清洁探针的清洁部件，所述清洁部件设置在所述壳体中，并且所述清洁部件包括支撑件，可拆卸地/可附接地联接到所述支撑件的安装支架和附接到所述安装支架的抛光垫，探针。

10. 发明申请

US20050264279A1 Wafer test equipment and method of aligning test equipment 失效
标题翻译：晶圆试验设备和对准试验设备的方法
公开(公告)号：US20050264279A1
公开(公告)日：2005-12-01
申请号：US11104337
申请日：2005-04-12
申请人： Jung-Nam Kim , Young-Jong Kim
发明人： Jung-Nam Kim , Young-Jong Kim
IPC分类号： H01L21/66 , G01R31/02 , G01R31/28
CPC分类号： G01R31/2891
摘要： Wafer test equipment comprises a probe station having a wafer chuck for supporting a wafer, a test head disposed on the probe station, a manipulator for moving the test head to and from an upper surface of the probe station, and an alignment monitoring member for monitoring an alignment of the test head docked to the probe station.
摘要翻译：晶片测试设备包括具有用于支撑晶片的晶片卡盘的探针台，设置在探测台上的测试头，用于将测试头移动到探测台的上表面和从测头的上表面移动的操纵器，以及用于监视的对准监视构件测试头对准到探测台的对准。

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