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1. 发明申请

US20090055579A1 Semiconductor memory device for simultaneously programming plurality of banks 审中-公开
标题翻译：用于同时编程多个存储体的半导体存储器件
公开(公告)号：US20090055579A1
公开(公告)日：2009-02-26
申请号：US12230142
申请日：2008-08-25
申请人： June-hong Park , Jae-yong Jeong , Chi-weon Yoon
发明人： June-hong Park , Jae-yong Jeong , Chi-weon Yoon
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C11/5628 , G11C16/10 , G11C2216/14
摘要： Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1st through n−1th sub program data, n being a natural number greater than 2.
摘要翻译：提供了一种用于同时编程多个存储体的半导体存储器件。半导体存储器件包括：包括多个存储体的存储单元阵列; 多个数据缓冲器，存储要在对应的存储体中编程的多个程序数据; 以及多个扫描锁存器，被配置为扫描从相应的数据缓冲器发送的多个节目数据，并且被配置为生成第1到第n个第1个子节目数据，n是大于2的自然数。

2. 发明授权

US10090046B2 Nonvolatile memory device and read method thereof 有权
公开(公告)号：US10090046B2
公开(公告)日：2018-10-02
申请号：US15341253
申请日：2016-11-02
申请人： Sang-Soo Park , June-Hong Park , Dongkyo Shim
发明人： Sang-Soo Park , June-Hong Park , Dongkyo Shim
IPC分类号： G11C11/34 , G11C11/56 , G11C16/28 , G11C16/10 , G11C16/08 , G11C29/02 , G11C29/52
摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

3. 发明申请

US20170133087A1 NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF 审中-公开
公开(公告)号：US20170133087A1
公开(公告)日：2017-05-11
申请号：US15341253
申请日：2016-11-02
申请人： Sang-Soo PARK , June-Hong PARK , Dongkyo SHIM
发明人： Sang-Soo PARK , June-Hong PARK , Dongkyo SHIM
IPC分类号： G11C11/56 , G11C16/28 , G11C16/08
CPC分类号： G11C11/5671 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/52
摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

4. 发明授权

US08189386B2 Non-volatile memory device and associated programming method using error checking and correction (ECC) 有权
标题翻译：非易失性存储器件和使用错误检查和校正（ECC）的相关编程方法
公开(公告)号：US08189386B2
公开(公告)日：2012-05-29
申请号：US12458437
申请日：2009-07-13
申请人： June-hong Park , Chi-weon Yoon
发明人： June-hong Park , Chi-weon Yoon
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621
摘要： A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation.
摘要翻译：用于非易失性存储器件的编程方法包括执行编程操作以对存储器单元进行编程，当编程存储器单元被确定为包括不能被编程的存储器单元以及当前程序循环是最大程序循环时，确定是否当编程失败的存储器单元的数量小于存储器的数量时，未编程的多个存储器单元对应于可以成功地进行ECC（错误校验和校正）的多个存储器单元可以成功进行ECC的单元，读取数据，以确定是否能够编程的存储器单元的错误位的数量是否能够成功地进行ECC，并且当未编程的存储器单元可以成功地进行ECC时，结束一个编程操作。

5. 发明申请

US20100027336A1 Non-volatile memory device and associated programming method using error checking and correction (ECC) 有权
标题翻译：非易失性存储器件和使用错误检查和校正（ECC）的相关编程方法
公开(公告)号：US20100027336A1
公开(公告)日：2010-02-04
申请号：US12458437
申请日：2009-07-13
申请人： June-hong Park , Chi-weon Yoon
发明人： June-hong Park , Chi-weon Yoon
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621
摘要： A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation.
摘要翻译：用于非易失性存储器件的编程方法包括执行编程操作以对存储器单元进行编程，当编程存储器单元被确定为包括不能被编程的存储器单元以及当前程序循环是最大程序循环时，确定是否当编程失败的存储器单元的数量小于存储器的数量时，未编程的多个存储器单元对应于可以成功地进行ECC（错误校验和校正）的多个存储器单元可以成功进行ECC的单元，读取数据，以确定是否能够编程的存储器单元的错误位的数量是否能够成功地进行ECC，并且当未编程的存储器单元可以成功地进行ECC时，结束一个编程操作。

6. 发明授权

US07489565B2 Flash memory device including multi-buffer block 失效
标题翻译：闪存设备包括多缓冲块
公开(公告)号：US07489565B2
公开(公告)日：2009-02-10
申请号：US11762797
申请日：2007-06-14
申请人： Ji-Ho Cho , Soo-Han Kim , June-Hong Park
发明人： Ji-Ho Cho , Soo-Han Kim , June-Hong Park
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1084 , G11C7/1087 , G11C7/1096 , G11C8/06 , G11C8/08 , G11C8/10 , G11C16/10 , G11C2207/104 , G11C2216/14
摘要： A flash memory device includes a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits includes a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.
摘要翻译：闪速存储器件包括存储单元阵列和临时存储要存储在存储单元阵列中的程序数据的多缓冲块，其中多缓冲块包括存储至少2个字的多个缓冲电路数据。每个缓冲电路包括多个寄存器，分别在至少2个字数据中存储两个相应的数据位，分别扫描对应于寄存器的逻辑，扫描逻辑数据中的第一个字数据的多个节目数据在第一扫描间隔期间的至少2字数据，并且在第二扫描期间，基于第一字数据的节目数据的数目，扫描至少2个字数据中的第二字数据的数目的数目间隔。

7. 发明申请

US20070297229A1 FLASH MEMORY DEVICE INCLUDING MULTI-BUFFER BLOCK 失效
标题翻译：闪存存储器件，包括多缓冲块
公开(公告)号：US20070297229A1
公开(公告)日：2007-12-27
申请号：US11762797
申请日：2007-06-14
申请人： Ji-Ho CHO , Soo-Han KIM , June-Hong PARK
发明人： Ji-Ho CHO , Soo-Han KIM , June-Hong PARK
IPC分类号： G11C14/00 , G11C11/34 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1084 , G11C7/1087 , G11C7/1096 , G11C8/06 , G11C8/08 , G11C8/10 , G11C16/10 , G11C2207/104 , G11C2216/14
摘要： A flash memory device comprises a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits comprises a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.
摘要翻译：闪速存储器件包括存储单元阵列和临时存储要存储在存储单元阵列中的程序数据的多缓冲块，其中多缓冲块包括存储至少2个字的多个缓冲电路数据。每个缓冲电路包括多个寄存器，分别在至少2个字数据中存储两个对应的数据位，分别对应于寄存器的扫描逻辑，其扫描第一字数据的多个程序数据在第一扫描间隔期间的至少2字数据，并且在第二扫描期间，基于第一字数据的节目数据的数目，扫描至少2个字数据中的第二字数据的数目的数目间隔。

8. 发明授权

US08929171B2 Voltage supply controller, nonvolatile memory device and memory system 有权
标题翻译：电压控制器，非易失性存储器件和存储器系统
公开(公告)号：US08929171B2
公开(公告)日：2015-01-06
申请号：US13571486
申请日：2012-08-10
申请人： June-Hong Park , Jin-Yub Lee
发明人： June-Hong Park , Jin-Yub Lee
IPC分类号： G11C11/4193 , G11C5/14 , G11C16/04 , G11C16/30 , G11C8/10
CPC分类号： G11C5/145 , G11C5/147 , G11C8/10 , G11C16/04 , G11C16/30
摘要： A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied.
摘要翻译：非易失性存储器件包括电压供应控制器（VSC），用于检测电源电压的电平并响应于此产生第一内部电压。当电源电压正常提供时，VSC提供等于外部高电压的第一内部电压，但是当电源电压异常供给时，VSC将第一内部电压提供到低于外部高电压的电平。

9. 发明申请

US20130114338A1 VOLTAGE SUPPLY CONTROLLER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译：电压供应控制器，非易失性存储器件和存储器系统
公开(公告)号：US20130114338A1
公开(公告)日：2013-05-09
申请号：US13571486
申请日：2012-08-10
申请人： JUNE-HONG PARK , JIN-YUB LEE
发明人： JUNE-HONG PARK , JIN-YUB LEE
IPC分类号： G11C5/14 , G11C16/30 , G11C16/04
CPC分类号： G11C5/145 , G11C5/147 , G11C8/10 , G11C16/04 , G11C16/30
摘要： A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied.
摘要翻译：非易失性存储器件包括电压供应控制器（VSC），用于检测电源电压的电平并响应于此产生第一内部电压。当电源电压正常提供时，VSC提供等于外部高电压的第一内部电压，但是当电源电压异常供给时，VSC将第一内部电压提供到低于外部高电压的电平。

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