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1. 发明申请

US20170125116A1 NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 有权
公开(公告)号：US20170125116A1
公开(公告)日：2017-05-04
申请号：US15340957
申请日：2016-11-01
申请人： Dongkyo SHIM , Sang-Soo PARK
发明人： Dongkyo SHIM , Sang-Soo PARK
IPC分类号： G11C16/34 , G11C16/10 , G11C16/04 , G11C16/08 , G11C16/16 , G11C16/26
CPC分类号： G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26
摘要： A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.

2. 发明授权

US09202587B2 Nonvolatile memory device, memory system comprising same, and method of programming same 有权
标题翻译：非易失性存储器件，包括其的存储器系统以及编程方法
公开(公告)号：US09202587B2
公开(公告)日：2015-12-01
申请号：US14278743
申请日：2014-05-15
申请人： Jonghoo Jo , Hyun Jun Yoon , Kitae Park , Dongkyo Shim
发明人： Jonghoo Jo , Hyun Jun Yoon , Kitae Park , Dongkyo Shim
IPC分类号： G11C11/34 , G11C16/34 , G11C16/10 , G11C16/04 , G11C16/08
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： A method of programming a nonvolatile memory device comprises performing an N-th program loop based on state data stored in data latches according to a default state ordering, determining whether conversion of the default state ordering is required according to a predetermined criterion, as a consequence of determining that conversion of the default state ordering is required, converting all or part of the state data stored in the data latches from the default state ordering to another state ordering, and performing a (N+1)th program loop based on the converted state data.
摘要翻译：一种非易失性存储器件的编程方法包括：根据默认状态顺序，根据存储在数据锁存器中的状态数据执行第N个程序循环，确定是否需要根据预定标准转换默认状态排序，结果确定需要转换默认状态排序，将存储在数据锁存器中的全部或部分状态数据从默认状态排序转换到另一状态排序，以及基于转换的第（N + 1）个程序循环执行状态数据。

3. 发明授权

US09368166B2 Nonvolatile memory devices, memory systems, and control methods using simultaneous recovery and output operations 有权
标题翻译：非易失性存储器件，存储器系统和使用同时恢复和输出操作的控制方法
公开(公告)号：US09368166B2
公开(公告)日：2016-06-14
申请号：US14153627
申请日：2014-01-13
申请人： Donghun Kwak , Hyun Jun Yoon , Dongkyo Shim
发明人： Donghun Kwak , Hyun Jun Yoon , Dongkyo Shim
IPC分类号： G11C7/10 , G11C16/26 , G11C16/04
CPC分类号： G11C7/22 , G11C7/10 , G11C7/1063 , G11C16/0483 , G11C16/26
摘要： A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.
摘要翻译：一种非易失性存储器件，包括一个单元阵列，该单元阵列包括在垂直方向上在基片上延伸的多个单元串，连接到多个位线的一个页缓冲器，并且被配置为在感测操作中存储该单元阵列的感测数据，发生器，其被配置为向多个字线和所述多个位线提供电压;以及输入/输出缓冲器，被配置为临时存储从所述页缓冲器接收的数据转储中的感测数据，并将所述临时存储的数据输出到外部设备。非易失性存储装置还包括控制逻辑，其被配置为在将感测数据转储到输入/输出缓冲器之后并且在从感测操作的偏置电压恢复单元阵列之前将非易失性存储器件的状态设置为就绪状态完成。

4. 发明申请

US20140204684A1 NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND RELATED CONTROL METHODS 有权
标题翻译：非易失性存储器件，存储器系统和相关控制方法
公开(公告)号：US20140204684A1
公开(公告)日：2014-07-24
申请号：US14153627
申请日：2014-01-13
申请人： DONGHUN KWAK , HYUN JUN YOON , DONGKYO SHIM
发明人： DONGHUN KWAK , HYUN JUN YOON , DONGKYO SHIM
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C7/10 , G11C7/1063 , G11C16/0483 , G11C16/26
摘要： A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.
摘要翻译：一种非易失性存储器件，包括一个单元阵列，该单元阵列包括在垂直方向上在基片上延伸的多个单元串，连接到多个位线的一个页缓冲器，并且被配置为在感测操作中存储该单元阵列的感测数据，发生器，其被配置为向多个字线和所述多个位线提供电压;以及输入/输出缓冲器，被配置为临时存储从所述页缓冲器接收的数据转储中的感测数据，并将所述临时存储的数据输出到外部设备。非易失性存储装置还包括控制逻辑，其被配置为在将感测数据转储到输入/输出缓冲器之后并且在从感测操作的偏置电压恢复单元阵列之前将非易失性存储器件的状态设置为就绪状态完成。

5. 发明授权

US10090046B2 Nonvolatile memory device and read method thereof 有权
公开(公告)号：US10090046B2
公开(公告)日：2018-10-02
申请号：US15341253
申请日：2016-11-02
申请人： Sang-Soo Park , June-Hong Park , Dongkyo Shim
发明人： Sang-Soo Park , June-Hong Park , Dongkyo Shim
IPC分类号： G11C11/34 , G11C11/56 , G11C16/28 , G11C16/10 , G11C16/08 , G11C29/02 , G11C29/52
摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

6. 发明申请

US20170133087A1 NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF 审中-公开
公开(公告)号：US20170133087A1
公开(公告)日：2017-05-11
申请号：US15341253
申请日：2016-11-02
申请人： Sang-Soo PARK , June-Hong PARK , Dongkyo SHIM
发明人： Sang-Soo PARK , June-Hong PARK , Dongkyo SHIM
IPC分类号： G11C11/56 , G11C16/28 , G11C16/08
CPC分类号： G11C11/5671 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/52
摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

7. 发明申请

US20150003152A1 STORAGE DEVICE AND A WRITE METHOD THEREOF 有权
标题翻译：存储设备及其写入方法
公开(公告)号：US20150003152A1
公开(公告)日：2015-01-01
申请号：US14188889
申请日：2014-02-25
申请人： DongHun KWAK , Dongkyo SHIM , KITAE PARK , Hyun-Wook PARK
发明人： DongHun KWAK , Dongkyo SHIM , KITAE PARK , Hyun-Wook PARK
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation.
摘要翻译：存储装置的写入方法包括响应于要执行粗略编程操作的确定，基于关于存储器件的存储器单元的信息来确定是否执行粗略的程序操作，通过执行存储器件中的程序数据粗程序操作和精细程序操作，并且响应于不执行粗程序操作的确定，通过执行精细程序操作来在存储器件中编程数据。

8. 发明申请

US20150049545A1 NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF PROGRAMMING SAME 有权
标题翻译：非易失性存储器件，包含其的存储器系统及其编程方法
公开(公告)号：US20150049545A1
公开(公告)日：2015-02-19
申请号：US14278743
申请日：2014-05-15
申请人： JONGHOO JO , HYUN JUN YOON , KITAE PARK , DONGKYO SHIM
发明人： JONGHOO JO , HYUN JUN YOON , KITAE PARK , DONGKYO SHIM
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： A method of programming a nonvolatile memory device comprises performing an N-th program loop based on state data stored in data latches according to a default state ordering, determining whether conversion of the default state ordering is required according to a predetermined criterion, as a consequence of determining that conversion of the default state ordering is required, converting all or part of the state data stored in the data latches from the default state ordering to another state ordering, and performing a (N+1)th program loop based on the converted state data.
摘要翻译：一种非易失性存储器件的编程方法包括：根据默认状态顺序，根据存储在数据锁存器中的状态数据执行第N个程序循环，确定是否需要根据预定标准转换默认状态排序，结果确定需要转换默认状态排序，将存储在数据锁存器中的全部或部分状态数据从默认状态排序转换到另一状态排序，以及基于转换的第（N + 1）个程序循环执行状态数据。

9. 发明授权

US08861276B2 Nonvolatile memory device, memory system comprising same, and method of operating same 有权
标题翻译：非易失性存储器件，包括其的存储器系统及其操作方法
公开(公告)号：US08861276B2
公开(公告)日：2014-10-14
申请号：US13527641
申请日：2012-06-20
申请人： Dongkyo Shim , Jaeyong Jeong , Ju Seok Lee , Ohsuk Kwon , Kitae Park , Hyunjun Yoon
发明人： Dongkyo Shim , Jaeyong Jeong , Ju Seok Lee , Ohsuk Kwon , Kitae Park , Hyunjun Yoon
IPC分类号： G11C16/26 , G11C16/04 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage.
摘要翻译：一种操作非易失性存储器件的方法包括从存储器控制器接收读取命令，确定非易失性存储器件的读取模式，基于读取模式选择读取电压，以及对所选择的页面的存储器单元执行读取操作使用所选择的读取电压的非易失性存储器件。

10. 发明申请

US20120327711A1 NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME 有权
标题翻译：非易失性存储器件，包含其的存储器系统及其操作方法
公开(公告)号：US20120327711A1
公开(公告)日：2012-12-27
申请号：US13527641
申请日：2012-06-20
申请人： DONGKYO SHIM , JAEYONG JEONG , JU SEOK LEE , OHSUK KWON , KITAE PARK , HYUNJUN YOON
发明人： DONGKYO SHIM , JAEYONG JEONG , JU SEOK LEE , OHSUK KWON , KITAE PARK , HYUNJUN YOON
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage.
摘要翻译：一种操作非易失性存储器件的方法包括从存储器控制器接收读取命令，确定非易失性存储器件的读取模式，基于读取模式选择读取电压，以及对所选择的页面的存储器单元执行读取操作使用所选择的读取电压的非易失性存储器件。

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