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1. 发明申请

US20160343434A1 SEMICONDUCTOR DEVICES INCLUDING AUXILIARY BIT LINES 有权
标题翻译：包括辅助位线的半导体器件
公开(公告)号：US20160343434A1
公开(公告)日：2016-11-24
申请号：US14969843
申请日：2015-12-15
申请人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
发明人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
IPC分类号： G11C13/00
CPC分类号： G11C13/0026 , G11C13/0004 , G11C13/0007 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/24 , H01L27/2454 , H01L27/2481
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括交替栅极和绝缘层的堆叠。半导体器件包括虚拟单元区域。半导体器件包括多个位线和多个辅助位线。多个辅助位线中的一些具有不同的相应长度。还提供了形成半导体器件的相关方法。

2. 发明授权

US09449870B2 Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby 有权
公开(公告)号：US09449870B2
公开(公告)日：2016-09-20
申请号：US14943532
申请日：2015-11-17
申请人： Dongseog Eun , Young-Ho Lee , Joonhee Lee , Seok-won Lee , Yoocheol Shin
发明人： Dongseog Eun , Young-Ho Lee , Joonhee Lee , Seok-won Lee , Yoocheol Shin
IPC分类号： H01L21/44 , H01L21/768 , H01L23/498 , H01L27/115 , H01L21/311 , H01L21/3213 , H01L21/441 , H01L27/24
CPC分类号： H01L23/498 , H01L21/31144 , H01L21/32139 , H01L21/441 , H01L21/76805 , H01L21/76877 , H01L23/49844 , H01L23/5226 , H01L27/11548 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

3. 发明授权

US09530789B2 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09530789B2
公开(公告)日：2016-12-27
申请号：US14701985
申请日：2015-05-01
申请人： Joonhee Lee , Jintaek Park
发明人： Joonhee Lee , Jintaek Park
IPC分类号： H01L27/115 , H01L29/792 , H01L29/423 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/4234 , H01L29/66833 , H01L29/7926
摘要： Semiconductor memory devices and methods of fabricating the same are provided. A semiconductor memory device includes stack gate structures that are spaced apart from each other in a first direction horizontal to a substrate. Each of the stack gate structures includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. Vertical channel structures penetrate the stack gate structures. A source plug line is provided between the stack gate structures. The source plug line is in contact with the substrate and extends in a second direction intersecting the first direction. The substrate being in contact with the source plug line includes a plurality of protruding regions formed along the second direction. Each of the protruding regions has a first width, and the protruding regions are spaced apart from each other by a first distance greater than the first width.
摘要翻译：提供半导体存储器件及其制造方法。一种半导体存储器件包括在与衬底水平的第一方向上彼此间隔开的堆叠栅极结构。堆叠栅极结构中的每一个包括绝缘层和栅极电极交替地且重复堆叠在基板上。垂直通道结构穿透堆叠门结构。在堆叠门结构之间提供源插头线。源插头线与衬底接触并沿与第一方向相交的第二方向延伸。与源插头线接触的衬底包括沿着第二方向形成的多个突起区域。每个突出区域具有第一宽度，并且突出区域彼此间隔开大于第一宽度的第一距离。

4. 发明申请

US20160099170A1 METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY 有权
标题翻译：形成电极堆叠的方法和三维半导体器件的制造方法
公开(公告)号：US20160099170A1
公开(公告)日：2016-04-07
申请号：US14943532
申请日：2015-11-17
申请人： Dongseog EUN , Young-Ho LEE , Joonhee LEE , Seok-won LEE , Yoocheol SHIN
发明人： Dongseog EUN , Young-Ho LEE , Joonhee LEE , Seok-won LEE , Yoocheol SHIN
IPC分类号： H01L21/768 , H01L27/24 , H01L21/3213 , H01L27/115 , H01L21/311
CPC分类号： H01L23/498 , H01L21/31144 , H01L21/32139 , H01L21/441 , H01L21/76805 , H01L21/76877 , H01L23/49844 , H01L23/5226 , H01L27/11548 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.
摘要翻译：提供了形成由此制造的电极堆叠和三维半导体器件的方法。该装置可以包括依次层叠在基板上以构成电极结构的电极。每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

5. 发明授权

US10276237B2 Semiconductor devices including auxiliary bit lines 有权
公开(公告)号：US10276237B2
公开(公告)日：2019-04-30
申请号：US15681910
申请日：2017-08-21
申请人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
发明人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
IPC分类号： H01L27/24 , G11C13/00
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

6. 发明申请

US20140054787A1 METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY 有权
标题翻译：形成电极堆叠的方法和三维半导体器件的制造方法
公开(公告)号：US20140054787A1
公开(公告)日：2014-02-27
申请号：US13973627
申请日：2013-08-22
申请人： Dongseog EUN , Young-Ho LEE , Joonhee LEE , Seok-won LEE , Yoocheol SHIN
发明人： Dongseog EUN , Young-Ho LEE , Joonhee LEE , Seok-won LEE , Yoocheol SHIN
IPC分类号： H01L23/498
CPC分类号： H01L23/498 , H01L21/31144 , H01L21/32139 , H01L21/441 , H01L21/76805 , H01L21/76877 , H01L23/49844 , H01L23/5226 , H01L27/11548 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.
摘要翻译：提供了形成由此制造的电极堆叠和三维半导体器件的方法。该装置可以包括依次层叠在基板上以构成电极结构的电极。每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

7. 发明申请

US20120181693A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120181693A1
公开(公告)日：2012-07-19
申请号：US13241741
申请日：2011-09-23
申请人： Jeeyong Kim , Jong-Hyun Park , Jin-Kyu Kang , Joonhee Lee
发明人： Jeeyong Kim , Jong-Hyun Park , Jin-Kyu Kang , Joonhee Lee
IPC分类号： H01L23/532
CPC分类号： H01L23/5226 , H01L21/76834 , H01L21/7685 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/53285 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include an upper interconnection on a substrate and an anti-reflection pattern disposed on the upper interconnection. The anti-reflection pattern may include a compound including a metal, carbon and nitrogen.
摘要翻译：半导体器件可以包括在衬底上的上互连和设置在上互连上的抗反射图案。抗反射图案可以包括包含金属，碳和氮的化合物。

8. 发明授权

US09773546B2 Semiconductor devices including auxiliary bit lines 有权
公开(公告)号：US09773546B2
公开(公告)日：2017-09-26
申请号：US14969843
申请日：2015-12-15
申请人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
发明人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0026 , G11C13/0004 , G11C13/0007 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/24 , H01L27/2454 , H01L27/2481
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

9. 发明申请

US20170207238A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20170207238A1
公开(公告)日：2017-07-20
申请号：US15403779
申请日：2017-01-11
申请人： Chang-Sup Lee , Sung-Hun Lee , Joonhee Lee , Seong Soon Cho
发明人： Chang-Sup Lee , Sung-Hun Lee , Joonhee Lee , Seong Soon Cho
IPC分类号： H01L27/11582 , H01L23/535 , H01L23/528 , H01L29/423 , H01L27/11556 , H01L23/522
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L29/42328 , H01L29/42344
摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

10. 发明授权

US09230904B2 Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby 有权
标题翻译：形成由此制造的电极堆叠和三维半导体器件的方法
公开(公告)号：US09230904B2
公开(公告)日：2016-01-05
申请号：US13973627
申请日：2013-08-22
申请人： Dongseog Eun , Young-Ho Lee , Joonhee Lee , Seok-won Lee , Yoocheol Shin
发明人： Dongseog Eun , Young-Ho Lee , Joonhee Lee , Seok-won Lee , Yoocheol Shin
IPC分类号： H01L23/48 , H01L23/498 , H01L27/115
CPC分类号： H01L23/498 , H01L21/31144 , H01L21/32139 , H01L21/441 , H01L21/76805 , H01L21/76877 , H01L23/49844 , H01L23/5226 , H01L27/11548 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.
摘要翻译：提供了形成由此制造的电极堆叠和三维半导体器件的方法。该装置可以包括依次层叠在基板上以构成电极结构的电极。每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

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