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1. 发明申请

US20080248757A1 Receiver Having a Gain-Controllable Stage 有权
标题翻译：具有增益控制级的接收器
公开(公告)号：US20080248757A1
公开(公告)日：2008-10-09
申请号：US12065315
申请日：2006-08-23
申请人： Johannes Brekelmans
发明人： Johannes Brekelmans
IPC分类号： H04B1/00
CPC分类号： H03G3/3052
摘要： A gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) comprises a reactive signal divider (CLN) followed by an amplifier arrangement (A1, A2 . . . , A7, ACC). The reactive signal divider (CLN) may be in the form of, for example, a capacitive ladder network. The gain-controllable stage (CLN, A1, A2 ..., A7, ACC) has a gain factor that depends on a signal division factor that the reactive signal divider (CLN) provides. The reactive signal divider (CLN) forms part of a filter (LC). The signal division factor is adjusted on the basis of a frequency (F) to which the receiver is tuned and a signal-strength indication (RS).
摘要翻译：增益可控级（CLN，A1，A2 ...，A7，ACC）包括一个无功信号分频器（CLN），后面是一个放大器装置（A1，A2 ... A7，ACC）。无功信号分配器（CLN）可以是例如电容梯形网络的形式。增益可控级（CLN，A1，A2 ...，A7，ACC）具有取决于无功信号分频器（CLN）提供的信号分配因子的增益因子。无功信号分频器（CLN）形成滤波器（LC）的一部分。基于接收机调谐的频率（F）和信号强度指示（RS）来调整信号分配因子。

2. 发明申请

US20060063503A1 Receiver and tuner with electronically tuned filter 审中-公开
标题翻译：接收器和调谐器与电子调谐滤波器
公开(公告)号：US20060063503A1
公开(公告)日：2006-03-23
申请号：US10517921
申请日：2002-05-27
申请人： Johannes Brekelmans
发明人： Johannes Brekelmans
IPC分类号： H04B1/18
CPC分类号： H03J1/0008 , H03J2200/28
摘要： Tuners (2) comprising electronically tuned filters (22,24) like varicap tuned coil-capacitor tank circuits need to be electronically calibrated, without receivers (1) being near. To store calibration signals, said tuners (2) need memories, which do not go well with high-frequency technology. By providing tuners (2) with identifiers for identifying database fields in databases (40) situated outside receivers (1), calibration signals resulting from calibration processes can be downloaded for calibrating the electronically tuned filter (22,24) after installment in the receiver (1) and without the tuner (2) requiring any memory. Preferably, the receiver (1) comprises a receiver memory (11) located outside the tuner (2) for storing the calibration signal after downloading, and the database (40) is coupled to a network (41), like the internet or an intranet, with the receiver (1) comprising an in/output to be coupled to the network (41), and with the database (40) being a server. The tuner (2) comprises a digital-to-analog converter (27,28) for converting the digital calibration signal into an analog calibration signal.
摘要翻译：包括电调谐滤波器（22,24）的调谐器（2），如变容二极管调谐线圈 - 电容器箱电路，需要进行电子校准，而没有接收器（1）靠近。为了存储校准信号，所述调谐器（2）需要存储器，这对于高频技术来说并不顺利。通过为调谐器（2）提供用于识别位于接收器（1）外部的数据库（40）中的数据库字段的标识符，可以下载校准过程产生的校准信号，以便在安装到接收器中之后校准电子调谐滤波器（22,24） 1），而没有调谐器（2）需要任何存储器。优选地，接收器（1）包括位于调谐器（2）外部的用于在下载之后存储校准信号的接收器存储器（11），并且数据库（40）耦合到网络（41），如互联网或内联网接收器（1）包括要耦合到网络（41）的输入/输出，并且数据库（40）是服务器。调谐器（2）包括用于将数字校准信号转换为模拟校准信号的数模转换器（27,28）。

3. 发明申请

US20070052451A1 DIFFERENTIAL INVERTER CIRCUIT 审中-公开
标题翻译：差分逆变器电路
公开(公告)号：US20070052451A1
公开(公告)日：2007-03-08
申请号：US11530092
申请日：2006-09-08
申请人： Johannes Brekelmans , Josephus Maria Kahlman , Gerben De Jong
发明人： Johannes Brekelmans , Josephus Maria Kahlman , Gerben De Jong
IPC分类号： H03K5/22
CPC分类号： H03F3/45179 , H03F3/3022 , H03F3/45748 , H03F3/45941 , H03F2203/30015 , H03F2203/45008 , H03F2203/45082 , H03F2203/45292 , H03F2203/45681
摘要： An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.
摘要翻译：一种改进的差分逆变器，包括具有用于接收第一输入信号和第二输入信号的差分输入的差分反相器，所述反相器还包括用于接收第一控制信号和第二控制信号的差分控制输入。改进的差分逆变器还包括用于发送第一输出信号和第二输出信号的差分输出。改进的差分逆变器还包括受控偏置发生器，其响应于偏置控制信号产生输入信号的第二矢量。控制偏置信号在耦合到差分逆变器的差分输出的分压器的输出处产生，所述偏置控制信号指示差分输出的直流电压。

4. 发明申请

US20060208801A1 Method of controlling a variable gain amplifier and electronic circuit 有权
标题翻译：控制可变增益放大器和电子电路的方法
公开(公告)号：US20060208801A1
公开(公告)日：2006-09-21
申请号：US10552817
申请日：2004-04-08
申请人： Johannes Brekelmans , Marc Notten
发明人： Johannes Brekelmans , Marc Notten
IPC分类号： H03G3/10
CPC分类号： H03G1/0088
摘要： The present invention relates to a method of controlling a variable gain amplifier having at least one semiconductor switch, the amplifier having a first gain when the semiconductor switch is in a first steady state and a first gate voltage is applied to the semiconductor switch, and the amplifier having a second gain when the semiconductor switch is in a second steady state and a second gate voltage is applied to the semiconductor switch, whereby a sequence of third gate voltages is applied to the semiconductor switch to transition between the first and second gains.
摘要翻译：本发明涉及一种控制具有至少一个半导体开关的可变增益放大器的方法，当半导体开关处于第一稳定状态并且第一栅极电压施加到半导体开关时，放大器具有第一增益，并且放大器，当半导体开关处于第二稳定状态并且第二栅极电压被施加到半导体开关时具有第二增益，由此一系列第三栅极电压被施加到半导体开关以在第一和第二增益之间转变。

5. 发明申请

US20060072393A1 Optical disk system with delay-difference detector without delay lines 失效
标题翻译：具有延迟差检测器的光盘系统，无延迟线
公开(公告)号：US20060072393A1
公开(公告)日：2006-04-06
申请号：US10523385
申请日：2003-07-21
申请人： Johannes Voorman , Gerben De Jong , Johannes Brekelmans
发明人： Johannes Voorman , Gerben De Jong , Johannes Brekelmans
IPC分类号： G11B7/00
CPC分类号： G11B7/131 , G11B7/0901
摘要： Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used. Said delay-difference detector (6) further comprises an analog adder/subtracter (9) for adding/subtracting sequential-logic circuit output signals and low pass filter(s) (10) located before or after said adder/subtracter (9).
摘要翻译：包括用于检测光盘的光检测器（1），包括用于检测分片放大检测信号中的延迟差的放大器和限幅器（2-5）和延迟差检测器（6），通过安装延迟无延迟差分检测器）包括类似反相器的组合逻辑电路（7,8），OR，NOR，AND，NAND和诸如SetResetFlipFlops的顺序逻辑电路（11-18）。在没有现有技术的延迟线的情况下，所述延迟差检测器（6）具有较低的复杂性并且成本低且可以很好地集成。通过引入用于检测上升沿之间的延迟差的第一对顺序逻辑电路（11,12,15,16）和用于检测下降沿之间的延迟差的第二对顺序逻辑电路（13,14,17,18）边缘，正在使用两种边缘，并且与仅使用一种边缘的情况相比，时间抖动的影响较小。所述延迟差检测器（6）还包括用于加/减顺序逻辑电路输出信号的模拟加法器/减法器（9）和位于所述加法器/减法器（9）之前或之后的低通滤波器（10）。

6. 发明申请

US20050286394A1 Means for limiting an output signal of an amplifier stage 失效
公开(公告)号：US20050286394A1
公开(公告)日：2005-12-29
申请号：US10531012
申请日：2003-09-19
申请人： Gerben De Jong , Johannes Brekelmans , Jozef Bergervoet
发明人： Gerben De Jong , Johannes Brekelmans , Jozef Bergervoet
IPC分类号： G11B7/005 , G11B7/125 , G11B7/13 , H03F1/32 , H03G7/06 , G11B7/00
CPC分类号： H03F1/32 , G11B7/0053 , G11B7/1263 , G11B7/13 , H03F1/3211 , H03G7/06
摘要： An electronic circuit is provided which can autonomously handle an input current (Ii) having a relatively wide dynamic range without being overdriven. The electronic circuit comprises an amplifier stage (AMPST) having an input (IP) for receiving the input current (Ii) and an output (OP) for supplying an output current (Io), such that, during operation, the strength of the output current (Io) increases in response to an increasing strength of the input current (Ii) as long as the strength of the input current (Ii) has not exceeded an input reference level. The strength of the output current (Io) is kept approximately constant when the strength of the input current (Ii) has exceeded the input reference level but has not exceeded a further input reference level. The strength of the output current (Io) decreases in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level. The amplifier stage (AMPST) may comprise a current mirror (CM) having an input which forms the input (IP), an output which forms the output (OP), and a common node (cn). The amplifier stage (AMPST) further comprises first control means (FCM) having an input connected to the input (EP), and an output connected to the common node (cn). First control means (FCM) controls a current (I2) to the common node (cn) and a voltage (Vcn) at the common node (cn). The first control means (FCM) comprises limiting means (LMT) for limiting the current (I2) when the value of the input current (Ii) has exceeded the input reference level. Then both the input and the output currents (Ii and Io) are limited. In order to avoid a saturation situation of a current source (Is) which supplies a current (I) to the input (EP), the amplifier stage (AMPST) may comprise second control means (SCM) for supplying a compensation current (ICMP) to the input (IP) when the input signal (Ii) has exceeded the input reference level. The current mirror (CM) comprises first (CP1) and second (CP2) current paths which form the core of the current mirror (CM), as is generally known. The decrease in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level is implemented by a third current path (CP3) which takes away current from the second current path (CP2). Optionally, to avoid that the value of the output current (Io) can become too low, a fourth current path (CP4) may be implemented which applies current to the second current path (CP2). The inventive electronic circuit may be advantageously applied in all electronic systems (like CD-apparatus) which need means to limit a maximum output signal.

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