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    • 3. 发明申请
    • Bit-detection arrangement and apparatus for reproducing information
    • 位检测装置和用于再现信息的装置
    • US20070008204A1
    • 2007-01-11
    • US10558712
    • 2004-05-25
    • Albertus Johannes Antonius RuttenNicolaas Maria Van BeurdenJosephus Maria KahlmanAlbert Immink
    • Albertus Johannes Antonius RuttenNicolaas Maria Van BeurdenJosephus Maria KahlmanAlbert Immink
    • H03M1/12
    • G11B20/10037G11B20/10009G11B20/1403H03L7/07H03L7/0994H04L7/0029H04L7/0334
    • Disclosed is a bit-detection arrangement able to convert an analog signal (AS) having an amplitude into a digital signal (DS) representing a bit sequence from which the analog signal (AS) is derived. The bit-detection arrangement has a phase detector which detect the phase difference between a quantized analog signal and a clock signal C2. The phase difference is sampled by an AD converter. The AD converter can sample at a relatively slow rate as the phase difference is a low frequency signal. The sampled phase difference is fed to a digital PLL which outputs a phase signal PHI. The phase signal and the quantized analog signal are used to recreate the digital signal (DS). The current invention is characterized in that the bit decision unit further comprises—at least one additional sample and hold unit SH2 able to sample the output signal S1, using a clock signal CSH2 and wherein the frequency of the clock signal CSH2 is equal to the frequency of clock signal CSH1 and the phase of clock signal CSH2 is substantially different from the phase of clock signal CSH1, and an output unit for outputting samples of either the sample and hold units SH1 or SH2, wherein the samples of the sample and hold unit SH1 are outputted when the phase signal PH1 indicates that the phase difference ΔP1 is in a first region and the samples of the additional sample and hold unit SH2 are outputted when the phase signal PH1 indicates that the phase difference ΔP1 is in a second region. This has the advantage that the change of bit errors occurring in the presence of phase jitter is reduced.
    • 公开了一种能够将具有振幅的模拟信号(AS)转换为表示从其中导出模拟信号(AS)的比特序列的数字信号(DS)的比特检测装置。 位检测装置具有检测量化模拟信号和时钟信号C 2 2之间的相位差的相位检测器。 相位差由AD转换器采样。 AD转换器可以以相对较慢的速率进行采样,因为相位差是低频信号。 采样相位差被馈送到输出相位信号PHI的数字PLL。 相位信号和量化的模拟信号用于重建数字信号(DS)。 本发明的特征在于,比特判定单元还包括能够使用时钟对至少一个附加的采样和保持单元SH 2采样输出信号S 1> 信号C SH2,并且其中时钟信号C SH2的频率等于时钟信号C SH1的频率和时钟信号的相位 C SH2 与时钟信号C SUB1 SH1的相位基本不同,以及用于输出采样和保持单元SH 1的采样的输出单元或SH <2>,其中当相位信号PH <1> 1时,采样和保持单元SH 1的样本被输出,表示相位差 当相位信号PH <1> <1>时,ΔP1 <1> 在第一区域中,并且附加采样和保持单元SH 2的样本被输出, 相位差ΔP1 <1>在第二区域中。 这具有如下优点:在存在相位抖动的情况下发生的位错误的变化被减少。