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1. 发明授权

US08166338B2 Reliable exception handling in a computer system 有权
标题翻译：计算机系统中可靠的异常处理
公开(公告)号：US08166338B2
公开(公告)日：2012-04-24
申请号：US12786981
申请日：2010-05-25
申请人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
发明人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/3861 , G06F11/073
摘要： A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.
摘要翻译：一种方法为计算机系统提供异常处理。由于检测到计算机系统硬件中的错误，因此确定了与硬件错误有关的异常向量，并将执行流传送到与异常向量相对应的调度器。选择主异常处理程序的多个实例的特定实例，并执行主异常处理程序的特定实例。因此，实际的异常处理程序包含两个不同的部分，一个调度程序，它是唯一的，最好位于一个安全的内存区域，一个主异常处理程序，它们的多个副本位于一个不安全的内存区域。

2. 发明申请

US20100313061A1 METHOD AND SYSTEM FOR RELIABLE EXCEPTION HANDLING IN A COMPUTER SYSTEM 有权
标题翻译：计算机系统中可靠的例外处理方法与系统
公开(公告)号：US20100313061A1
公开(公告)日：2010-12-09
申请号：US12786981
申请日：2010-05-25
申请人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
发明人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
IPC分类号： G06F11/07 , G06F12/06 , G06F12/02 , G06F12/08
CPC分类号： G06F11/0793 , G06F9/3861 , G06F11/073
摘要： A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.
摘要翻译：一种方法为计算机系统提供异常处理。由于检测到计算机系统硬件中的错误，因此确定了与硬件错误有关的异常向量，并将执行流传送到与异常向量相对应的调度器。选择主异常处理程序的多个实例的特定实例，并执行主异常处理程序的特定实例。因此，实际的异常处理程序包含两个不同的部分，一个调度程序，它是唯一的，最好位于一个安全的内存区域，一个主异常处理程序，它们的多个副本位于一个不安全的内存区域。

3. 发明授权

US08954721B2 Multi-chip initialization using a parallel firmware boot process 有权
标题翻译：使用并行固件引导过程进行多芯片初始化
公开(公告)号：US08954721B2
公开(公告)日：2015-02-10
申请号：US13314733
申请日：2011-12-08
申请人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
发明人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177 , G06F15/00 , G06F15/167
CPC分类号： G06F9/4405 , G06F9/4401 , G06F9/4403 , G06F9/44505 , G06F12/00
摘要： Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.
摘要翻译：提供了在多芯片数据处理系统中用于执行用于引导多芯片数据处理系统的多个处理器芯片中的每一个的引导过程的机制。利用这些机制，并行地执行多芯片不可知的隔离引导相位操作，以执行多个处理器芯片中的每一个的初始启动，就好像每个处理器芯片是多芯片数据中的唯一处理器芯片处理系统。并行执行每个处理器芯片的多芯片感知隔离引导阶段操作，其中每个处理器芯片具有其自己独立配置的地址空间。此外，执行统一配置阶段操作以从多个处理器芯片中选择主处理器芯片，并且配置多个处理器芯片中的其他处理器芯片作为由主处理器芯片控制的从处理器芯片。

4. 发明申请

US20130060986A1 INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY 有权
公开(公告)号：US20130060986A1
公开(公告)日：2013-03-07
申请号：US13226360
申请日：2011-09-06
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/36
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

5. 发明授权

US08954639B2 Integrated link calibration and multi-processor topology discovery 有权
标题翻译：集成链路校准和多处理器拓扑发现
公开(公告)号：US08954639B2
公开(公告)日：2015-02-10
申请号：US13226360
申请日：2011-09-06
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/00 , G06F9/00
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.
摘要翻译：在多处理器系统中将链路校准和动态拓扑发现集成在多处理器系统中建立多个处理器中的第一个作为集成链路校准和动态拓扑发现的指导者。多个高速互连将多个处理器彼此连接。导向器处理器经由共享硬件资源引导多个高速互连中的每一个的校准。共享硬件资源在多个处理器之间共享。基于被校准的多个高速互连中的每一个的结果来校准多个高速互连中的每一个来增量地发现多处理器系统的拓扑。

6. 发明申请

US20130151829A1 Multi-Chip Initialization Using a Parallel Firmware Boot Process 有权
公开(公告)号：US20130151829A1
公开(公告)日：2013-06-13
申请号：US13314733
申请日：2011-12-08
申请人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
发明人： Eberhard Amann , Frank Haverkamp , Thomas Huth , Jan Kunigk
IPC分类号： G06F9/00
CPC分类号： G06F9/4405 , G06F9/4401 , G06F9/4403 , G06F9/44505 , G06F12/00
摘要： Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

7. 发明申请

US20130060978A1 INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY 审中-公开
标题翻译：综合链接校准和多处理器拓扑学发现
公开(公告)号：US20130060978A1
公开(公告)日：2013-03-07
申请号：US13592406
申请日：2012-08-23
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.
摘要翻译：在多处理器系统中将链路校准和动态拓扑发现集成在多处理器系统中建立多个处理器中的第一个作为集成链路校准和动态拓扑发现的指导者。多个高速互连将多个处理器彼此连接。导向器处理器经由共享硬件资源引导多个高速互连中的每一个的校准。共享硬件资源在多个处理器之间共享。基于被校准的多个高速互连中的每一个的结果来校准多个高速互连中的每一个来增量地发现多处理器系统的拓扑。

8. 发明授权

US08996770B2 Integrated link calibration and multi-processor topology discovery 有权
公开(公告)号：US08996770B2
公开(公告)日：2015-03-31
申请号：US13592406
申请日：2012-08-23
申请人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
发明人： Eberhard Amann , Frank Haverkamp , Jan Kunigk , Thomas Huth
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F15/177
摘要： Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

9. 发明授权

US08467526B2 Key evolution method and system of block ciphering 失效
标题翻译：块加密的关键演进方法和系统
公开(公告)号：US08467526B2
公开(公告)日：2013-06-18
申请号：US12135576
申请日：2008-06-09
申请人： Jan Kunigk , Sinja Kunigk , Sven Lukas
发明人： Jan Kunigk , Sinja Kunigk , Sven Lukas
IPC分类号： H04K1/00 , H04K1/06 , H04L9/00 , H04L9/28
CPC分类号： H04L9/0631
摘要： A system and associated method for block ciphering. The method generates a key that is specific to a text block being encrypted and later being decrypted. The text block is encrypted by a block cipher encryption with the key. The encrypted text block is decrypted by a block cipher decryption with the key back to the text block. Altering a single bit in either the encrypted text block or the key results in unsuccessful decryption such that a decrypted text block is completely different from the before encryption.
摘要翻译：一种用于块加密的系统和相关方法。该方法生成一个特定于被加密并随后被解密的文本块的密钥。文本块通过密钥加密密码加密。加密的文本块通过使用密钥的块密码解密解密到文本块。在加密文本块或密钥中改变单个位导致解密失败，使得解密的文本块与之前的加密完全不同。

10. 发明申请

US20090304180A1 KEY EVOLUTION METHOD AND SYSTEM OF BLOCK CIPHERING 失效
标题翻译：关键演化方法和块体系统
公开(公告)号：US20090304180A1
公开(公告)日：2009-12-10
申请号：US12135576
申请日：2008-06-09
申请人： Jan Kunigk , Sinja Kunigk , Sven Lukas
发明人： Jan Kunigk , Sinja Kunigk , Sven Lukas
IPC分类号： H04L9/28 , H04L9/06
CPC分类号： H04L9/0631
摘要： A system and associated method for block ciphering. The method generates a key that is specific to a text block being encrypted and later being decrypted. The text block is encrypted by a block cipher encryption with the key. The encrypted text block is decrypted by a block cipher decryption with the key back to the text block. Altering a single bit in either the encrypted text block or the key results in unsuccessful decryption such that a decrypted text block is completely different from the before encryption.
摘要翻译：一种用于块加密的系统和相关方法。该方法生成一个特定于被加密并随后被解密的文本块的密钥。文本块通过密钥加密密码加密。加密的文本块通过使用密钥的块密码解密解密到文本块。在加密文本块或密钥中改变单个位导致解密失败，使得解密的文本块与之前的加密完全不同。

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