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1. 发明授权

US4807147A Sampling wave-form digitizer for dynamic testing of high speed data conversion components 失效
标题翻译：采样波形数字化仪，用于高速数据转换组件的动态测试
公开(公告)号：US4807147A
公开(公告)日：1989-02-21
申请号：US804224
申请日：1985-11-27
申请人： Joel M. Halbert , Myron J. Koen
发明人： Joel M. Halbert , Myron J. Koen
IPC分类号： G01R31/28 , H03M1/00 , G06F15/31 , G01R23/16
CPC分类号： G01R31/2834 , H03M1/1255
摘要： A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The sampling waveform digitizer system comprises a sampling comparator for comparing a sampled input signal with a first signal. An integrator coupled to the comparator provides an output signal from the integrator and becomes the first signal. An analog to digital converter provides the digital representation of the analog waveform. A controllable delay is provided for selecting a period of time for sampling the input signal by the comparator. A control device is provided for controlling the time the comparator samples the input signal. These combination of system features allow the digitizer to receive high speed analog waveforms and convert them to an accurate digital representation of the previously described high speed analog waveform.
摘要翻译：提供了可扩展用于高速数据转换组件的动态测试的采样数字化仪系统。采样波形数字转换器系统包括用于将采样的输入信号与第一信号进行比较的采样比较器。耦合到比较器的积分器提供来自积分器的输出信号，并成为第一信号。模数转换器提供模拟波形的数字表示。提供了可控延迟，用于选择由比较器对输入信号进行采样的时间段。提供控制装置用于控制比较器对输入信号进行采样的时间。这些系统特性的组合使得数字化仪可以接收高速模拟波形，并将其转换成前述高速模拟波形的精确数字表示。

2. 发明授权

US07345542B2 Circuit and method for avoiding circuit performance degradation caused by time-variable thermal imbalances 有权
标题翻译：用于避免由时变热失衡引起的电路性能下降的电路和方法
公开(公告)号：US07345542B2
公开(公告)日：2008-03-18
申请号：US11311735
申请日：2005-12-19
申请人： Ahmad Dashtestani , Joel M. Halbert
发明人： Ahmad Dashtestani , Joel M. Halbert
IPC分类号： H03F3/45
CPC分类号： H03F3/45977 , H03F3/45085 , H03F3/45094 , H03F3/45475 , H03F3/456 , H03F3/45973 , H03F2203/45654 , H03F2203/45674
摘要： A signal processing circuit includes a circuit stage for operating on signals in a signal path of an input signal, including main circuitry for operating on relatively small-value signals and alternative circuitry for amplifying/processing signals during a condition which otherwise would cause thermal imbalance in the main circuitry. The circuit stage includes switching circuitry for coupling signals in the signal path of the input signal to the main input circuitry during normal small-signal operating conditions and for coupling signals in the signal path of the input signal to the alternative circuitry during the condition which otherwise would cause thermal imbalance in the main circuitry.
摘要翻译：信号处理电路包括用于对输入信号的信号路径中的信号进行操作的电路级，包括用于在相对较小值信号上操作的主电路和用于在否则将导致热失衡的情况下放大/处理信号的替代电路主电路。电路级包括用于在正常小信号操作条件期间将输入信号的信号路径中的信号耦合到主输入电路的开关电路，并且用于在输入信号的信号路径中将信号耦合到替代电路，将导致主电路中的热不平衡。

3. 发明授权

US07236055B2 Differential amplifier circuit and method for reducing thermally induced offsets caused by large differential signals 有权
标题翻译：差分放大器电路和减小由大差分信号引起的热感偏移的方法
公开(公告)号：US07236055B2
公开(公告)日：2007-06-26
申请号：US11032254
申请日：2005-01-10
申请人： Joel M. Halbert , Ahmad Dashtestani
发明人： Joel M. Halbert , Ahmad Dashtestani
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45085 , H03F3/45094 , H03F3/456 , H03F3/45973 , H03F3/45977 , H03F2203/45654 , H03F2203/45674
摘要： An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).
摘要翻译：放大器包括具有用于放大差分输入信号（Vin）的输入级（20）的差分放大器（10）和耦合到输入级（20）的用于产生和输出信号（Vout）的输出级（6）。输入级（20）包括用于放大输入信号（Vin）的小信号值的主输入电路（20A）和用于在导致热不平衡的条件期间放大输入信号（Vin）的替代输入电路（20B）主输入电路（20B）。输入级（20）包括用于在正常小信号操作条件期间将输入信号（Vin）耦合到主输入电路（20A）的开关电路（12），并且在大信号期间将输入信号（Vin）耦合到替代输入电路（20A）导致主输入电路（20B）热不平衡的工作条件。

4. 发明授权

US06504419B1 High-speed closed loop switch and method for video and communications signals 有权
标题翻译：高速闭环开关及视频和通信信号的方法
公开(公告)号：US06504419B1
公开(公告)日：2003-01-07
申请号：US09819246
申请日：2001-03-28
申请人： Paul G. Damitio , Joel M. Halbert
发明人： Paul G. Damitio , Joel M. Halbert
IPC分类号： H03K1762
CPC分类号： H03K17/04213 , H03K17/6257
摘要： A circuit for multiplexing a selected one of a plurality of input signals to an output conductor includes a plurality of diamond follower input buffers each having an input terminal coupled to receive an input signal, respectively. A diamond follower output buffer has an output coupled to the output conductor. A feedback resistor is coupled between the output conductor and the outputs of the input buffers. A first current mirror has a control input coupled to a first current bias terminal of each input buffer, and a second current error has a control input coupled to a second current bias terminal of each input buffer. The first and second current mirrors have outputs connected to drive the input of the output buffer and bias current terminals of the output buffer to provide a high slew rate.
摘要翻译：用于将多个输入信号中选择的一个输入信号多路复用到输出导体的电路包括多个金刚石跟随器输入缓冲器，每个具有耦合以输入信号的输入端。金刚石跟随器输出缓冲器具有耦合到输出导体的输出。反馈电阻耦合在输出导体和输入缓冲器的输出之间。第一电流镜具有耦合到每个输入缓冲器的第一电流偏置端子的控制输入，并且第二电流误差具有耦合到每个输入缓冲器的第二电流偏置端子的控制输入。第一和第二电流镜具有连接的输出以驱动输出缓冲器的输入端和输出缓冲器的偏置电流端子以提供高转换速率。

5. 发明授权

US06278326B1 Current mirror circuit 有权
标题翻译：电流镜电路
公开(公告)号：US06278326B1
公开(公告)日：2001-08-21
申请号：US09692370
申请日：2000-10-19
申请人： Kenneth W. Murray , Joel M. Halbert
发明人： Kenneth W. Murray , Joel M. Halbert
IPC分类号： H03F304
CPC分类号： H03F3/3079 , H03F3/3066 , H03F3/3076 , H03F3/3081 , H03F3/343 , H03F3/45139 , H03F3/45152 , H03F3/45475 , H03F3/45502 , H03F3/4556 , H03F3/456 , H03F3/45609 , H03F3/45937
摘要： A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.
摘要翻译：根据本发明的电流镜电路克服了现有技术的许多缺点。用于提供电流参考信号的电流镜电路适当地包括至少一个退化电阻器，以为较低电压噪声提供更多的退化，同时还包括至少一个钳位装置以防止电流镜的饱和。钳位装置适当地包括至少一个二极管，例如肖特基型二极管。此外，夹持装置可以适当地构造成有助于电流镜电路的更高的转换速率。

6. 发明授权

US5627495A Topography for integrated circuit operational amplifier 失效
标题翻译：集成电路运算放大器的地形图
公开(公告)号：US5627495A
公开(公告)日：1997-05-06
申请号：US534039
申请日：1995-09-26
申请人： Joel M. Halbert , Kenneth W. Murray
发明人： Joel M. Halbert , Kenneth W. Murray
IPC分类号： H03F3/30 , H03F3/45 , H03F1/30
CPC分类号： H03F3/4521 , H03F3/3076 , H03F3/45094 , H03F2203/45028 , H03F2203/45366 , H03F2203/45371 , H03F2203/45392
摘要： A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. Low gain amplification circuit transistors are located adjacent to the low gain differential input circuit and disposed along the thermal centerline between the low gain differential input circuit and the output drive circuit stage to provide approximately balanced response to the low gain amplification circuit transistors to differential heating by the output driver circuit. Compensated bias current circuitry is located along the fourth edge and adjacent to the low gain amplification circuit transistors and the output driver circuit.
摘要翻译：具有第一，第二，第三和第四连续边缘的高速集成电路运算放大器芯片包括平行于第二和第四边缘的热中心线。输出驱动器电路沿着第三边缘位于输出接合焊盘附近并且围绕热中心线大致对称地设置，以提供运算放大器芯片相对于热中心线的近似平衡的差分加热。低增益差分输入电路位于第一边缘附近并且围绕热中心线大致对称地设置，以将低增益差分输入电路中的匹配晶体管的大致平衡的响应提供给由差分加热产生的等温线。低增益放大电路晶体管位于低增益差分输入电路附近，并沿着低增益差分输入电路和输出驱动电路级之间的热中心线设置，以向低增益放大电路晶体管提供近似平衡的响应，以通过输出驱动电路。补偿偏置电流电路沿着第四边缘并且邻近低增益放大电路晶体管和输出驱动器电路。

7. 发明授权

US4777470A High speed successive approximation register in analog-to-digital converter 失效
标题翻译：模数转换器中的高速逐次逼近寄存器
公开(公告)号：US4777470A
公开(公告)日：1988-10-11
申请号：US101760
申请日：1987-09-28
申请人： Jimmy R. Naylor , Joel M. Halbert , Wallace Burney
发明人： Jimmy R. Naylor , Joel M. Halbert , Wallace Burney
IPC分类号： H03M1/38 , H03M1/00 , H03M1/46
CPC分类号： H03M1/42 , H03M1/46
摘要： In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate. Beginning with the most significant bit (MSB), each successive digital approximation number applied to the DAC consists of a "1" gated to the DAC by the shift register bit presently containing the propagating "0". After the present digital approximation number has been compared (by a comparator) to the analog input current, the resulting comparator data is latched into the data latch as the "0" shifts to the next bit. When the procedure has been completed for all N bits, the N bit word stored in the N data latches accurately represents the analog input current.
摘要翻译：在逐次逼近模拟数字转换器中，逐次逼近寄存器（SAR）包括一个N位边缘触发移位寄存器，每个位包括一个主从触发器。每个移位寄存器位的输出被施加到D型锁存器的锁存器输入和执行逻辑“与”功能的双输入门的一个输入。门的另一个输入端连接到锁存器的输出端。 N个锁存器中的每一个的D输入端连接到对应的比较器的输出，该比较器响应于由N位数模转换器（DAC）产生的逐次逼近数，将模拟输入信号与由N位数模转换器（DAC）产生的信号进行比较特区门输出连接到DAC的数字输入。 A“0”以DAC转换速率传播通过移位寄存器。从最高有效位（MSB）开始，施加到DAC的每个连续的数字近似值由当前包含传播“0”的移位寄存器位选通到DAC的“1”组成。在将当前数字近似值（由比较器）与模拟输入电流进行比较之后，当“0”移位到下一位时，所得到的比较器数据被锁存到数据锁存器中。当所有N位完成程序时，存储在N个数据锁存器中的N位字准确地表示模拟输入电流。

8. 发明授权

US06429744B2 Method for bias rail buffering 有权
标题翻译：斜轨缓冲方法
公开(公告)号：US06429744B2
公开(公告)日：2002-08-06
申请号：US09904806
申请日：2001-07-13
申请人： Kenneth W. Murray , Joel M. Halbert
发明人： Kenneth W. Murray , Joel M. Halbert
IPC分类号： H03F326
CPC分类号： H03F3/3079 , H03F3/3066 , H03F3/3076 , H03F3/3081 , H03F3/343 , H03F3/45139 , H03F3/45152 , H03F3/45475 , H03F3/45502 , H03F3/4556 , H03F3/456 , H03F3/45609 , H03F3/45937
摘要： A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.
摘要翻译：根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号。偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰。

9. 发明授权

US4641246A Sampling waveform digitizer for dynamic testing of high speed data conversion components 失效
公开(公告)号：US4641246A
公开(公告)日：1987-02-03
申请号：US543853
申请日：1983-10-20
申请人： Joel M. Halbert , Myron J. Koen
发明人： Joel M. Halbert , Myron J. Koen
IPC分类号： G01R29/00 , G01R13/34 , G01R31/28 , H03M1/00 , H03M1/12 , G01R23/16 , G06F15/31
CPC分类号： H03M1/1071 , G01R31/2834 , H03M1/66
摘要： A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The system includes latching comparators which are supplied with the waveform under test and the comparator digital output is integrated by an operational amplifier integrator and fed back to the reference input of the latching comparator to form a comparator-integrator loop. A circuit provides strobe pulses which repeatedly sample the latch enable input of the comparators at a selected time/point until the integrator feedback forces the comparator reference input to be equal to the sample value of the input signal. At this point, an equilibrium state is reached where the integrator output oscillates about the sampled value, and when the loop settles, an analog-to-digital converter reads the final value under computer command. The sample point is computer controlled through a programmable delay line. A modified T-filter system operatively coupled between the output of the latching comparator and the input of the operational amplifier allows control of the integrator slope and filters out signal spikes to allow the required accuracy for high speed measurements while a similar modified T-filter is provided in the feedback loop for preventing disturbances at the integrator output which could be caused by the sampling of the latching comparators and for simultaneously preventing ringing and for rounding off signal spikes in the feedback loop. Various adaptions of the broad sampling digitizer system are provided for measuring the settling time of a 12-bit digital-to-analog converter whose common mode output reading is one-half LSB accuracy in under 40 nanoseconds and a dynamic tester for very fast-acting sample and hold amplifier circuits which measure, by independently controlling the polarity of the square wave or test stimulus signal and the polarity of the hold select command, such circuit parameters as acquisition time, sample-to-hold settling time, sample-to-hold offset, glitch amplitude, amplitude delay, hold mode feedthrough rejection, risetime, slew rate, and the like.

10. 发明授权

US06297699B1 Bias rail buffer circuit and method 有权
标题翻译：偏置轨道缓冲电路及方法
公开(公告)号：US06297699B1
公开(公告)日：2001-10-02
申请号：US09692017
申请日：2000-10-19
申请人： Kenneth W. Murray , Joel M. Halbert
发明人： Kenneth W. Murray , Joel M. Halbert
IPC分类号： H03F326
CPC分类号： H03F3/3079 , H03F3/3066 , H03F3/3076 , H03F3/3081 , H03F3/343 , H03F3/45139 , H03F3/45152 , H03F3/45475 , H03F3/45502 , H03F3/4556 , H03F3/456 , H03F3/45609 , H03F3/45937
摘要： A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.
摘要翻译：根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号。偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰。

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