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1. 发明申请

US20090039961A1 Low quiescent current output stage and method with improved output drive 有权
标题翻译：低静态电流输出级和改进输出驱动方式
公开(公告)号：US20090039961A1
公开(公告)日：2009-02-12
申请号：US11890682
申请日：2007-08-07
申请人： Paul G. Damitio
发明人： Paul G. Damitio
IPC分类号： H03G3/30
CPC分类号： H03F1/307 , H03F1/0261 , H03F3/3069 , H03F2203/30015 , H03F2203/30147 , H03F2203/30153
摘要： Circuitry for increasing the maximum output current magnitude of a diamond buffer (Q57,58,74,75) having increased maximum output current provides a bias current of a first magnitude (I) into an emitter of a PNP first input transistor (Q57) and sinks a bias current of the first magnitude out of an emitter of an NPN second input transistor (Q55). The decrease is sensed in a collector current of the first input transistor caused by a demand for increased base current by a NPN first output transistor (Q74) of the diamond buffer. A collector current (Ic(65)) in a NPN first transistor (Q65) is increased in response to the decrease in the collector current of the first input transistor. The increased collector current in the first transistor is mirrored into a base of the first output transistor to boost its base current and maintain operation of the first input transistor when the amount of base current demanded by the first output transistor exceeds the first magnitude.
摘要翻译：增加具有增加的最大输出电流的金刚石缓冲器的最大输出电流幅度（Q57,58,74,75）的电路提供第一幅度（I）到PNP第一输入晶体管（Q57）的发射极的偏置电流，并且从NPN第二输入晶体管（Q55）的发射极吸收第一幅度的偏置电流。由于由金刚石缓冲器的NPN第一输出晶体管（Q74）增加的基极电流的需求引起的，在第一输入晶体管的集电极电流中感测到该减小。 NPN第一晶体管（Q65）中的集电极电流（Ic（65））响应于第一输入晶体管的集电极电流的减小而增加。当第一输出晶体管所需的基极电流量超过第一幅度时，第一晶体管中增加的集电极电流被镜像到第一输出晶体管的基极中，以提升其基极电流并保持第一输入晶体管的工作。

2. 发明授权

US08188790B1 Gated class H amplifier/line driver system and method 有权
标题翻译：门控级H放大器/线驱动器系统及方法
公开(公告)号：US08188790B1
公开(公告)日：2012-05-29
申请号：US12928468
申请日：2010-12-13
申请人： Paul G. Damitio , Xavier P. Ramus , He Qing
发明人： Paul G. Damitio , Xavier P. Ramus , He Qing
IPC分类号： H03G3/20
CPC分类号： H03F3/21 , H03F1/0222 , H03F2200/321
摘要： Amplifier circuitry (10) includes a driver amplifier (11) and an integrator amplifier (AH) producing an output signal (VAH) that controls a pass transistor (Q2) coupled to a pump capacitor (CH). Input circuitry (16) controls the direction of ramping of the output signal during a first interval to boost a supply voltage (V12) of the driver amplifier via the pump capacitor, and also controls the direction of ramping to recharge the pump capacitor following a second interval. In one embodiment, pump capacitor recharging circuitry (Q75,R76,ICCH) completes the recharging of the pump capacitor following the second interval after it has been partially recharged by the integrator amplifier.
摘要翻译：放大器电路（10）包括驱动放大器（11）和积分放大器（AH），其产生控制耦合到泵电容器（CH）的通过晶体管（Q2）的输出信号（VAH）。输入电路（16）在第一间隔期间控制输出信号的斜坡方向，以经由泵电容器升高驱动放大器的电源电压（V12），并且还控制斜坡的方向以在第二时间之后对泵电容器再充电间隔。在一个实施例中，泵电容器充电电路（Q75，R76，ICCH）在其由积分放大器部分再充电之后的第二间隔之后完成泵电容器的再充电。

3. 发明授权

US06504419B1 High-speed closed loop switch and method for video and communications signals 有权
标题翻译：高速闭环开关及视频和通信信号的方法
公开(公告)号：US06504419B1
公开(公告)日：2003-01-07
申请号：US09819246
申请日：2001-03-28
申请人： Paul G. Damitio , Joel M. Halbert
发明人： Paul G. Damitio , Joel M. Halbert
IPC分类号： H03K1762
CPC分类号： H03K17/04213 , H03K17/6257
摘要： A circuit for multiplexing a selected one of a plurality of input signals to an output conductor includes a plurality of diamond follower input buffers each having an input terminal coupled to receive an input signal, respectively. A diamond follower output buffer has an output coupled to the output conductor. A feedback resistor is coupled between the output conductor and the outputs of the input buffers. A first current mirror has a control input coupled to a first current bias terminal of each input buffer, and a second current error has a control input coupled to a second current bias terminal of each input buffer. The first and second current mirrors have outputs connected to drive the input of the output buffer and bias current terminals of the output buffer to provide a high slew rate.
摘要翻译：用于将多个输入信号中选择的一个输入信号多路复用到输出导体的电路包括多个金刚石跟随器输入缓冲器，每个具有耦合以输入信号的输入端。金刚石跟随器输出缓冲器具有耦合到输出导体的输出。反馈电阻耦合在输出导体和输入缓冲器的输出之间。第一电流镜具有耦合到每个输入缓冲器的第一电流偏置端子的控制输入，并且第二电流误差具有耦合到每个输入缓冲器的第二电流偏置端子的控制输入。第一和第二电流镜具有连接的输出以驱动输出缓冲器的输入端和输出缓冲器的偏置电流端子以提供高转换速率。

4. 发明申请

US20090058525A1 Common-mode bandwidth reduction circuit and method for differential applications 有权
标题翻译：共模带宽降低电路和差分应用的方法
公开(公告)号：US20090058525A1
公开(公告)日：2009-03-05
申请号：US11903105
申请日：2007-09-20
申请人： Paul G. Damitio , Ahmad Dashtestani
发明人： Paul G. Damitio , Ahmad Dashtestani
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/45475 , H03F3/45479 , H03F3/45968 , H03F2203/45048 , H03F2203/45356 , H03F2203/45392 , H03F2203/45394 , H03F2203/45588 , H03F2203/45681 , H03F2203/45726
摘要： An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT 1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively. Lower bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (16-1) and second (16-2) lower current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (14-2) and first (14-1) upper current mirrors, respectively, to oppose signals at the inputs (IN) of the current mirrors in response to the common mode input signal.
摘要翻译：放大器驱动器电路（10）分别包括第一（11-1）和第二（11-2）个反馈放大器，分别包括第一（14-1）和第二（14-2）上电流镜，第一（16-1）和第二（16-2）个下电流镜，第一（12-1）和第二（12-2））放大器输入级接收共模输入信号，以及第一（18-1）和第二（18-2）放大器输出级分别耦合到第一和第二放大器输入级的输出。每个电流镜具有输入（IN）和第一（OUT 1）和第二（OUT2）输出。第一（12-1）和第二（12-2）放大器输入级的上偏置端分别耦合到第一（14-1）和第二（14-2）上电流镜的输入（IN）并分别交叉耦合到第二（16-2）和第一（16-1）下电流镜的第二输出端（OUT2）。第一（12-1）和第二（12-2）放大器输入级的低偏置端分别耦合到第一（16-1）和第二（16-2）下电流镜的输入（IN）并且分别与第二（14-2）和第一（14-1）上电流镜的第二输出（OUT2）交叉耦合，以与当前反射镜的输入（IN）响应于相应于共模输入信号。

5. 发明授权

US07102440B2 High output current wideband output stage/buffer amplifier 有权
标题翻译：高输出电流宽带输出级/缓冲放大器
公开(公告)号：US07102440B2
公开(公告)日：2006-09-05
申请号：US10856140
申请日：2004-05-28
申请人： Paul G. Damitio , Sergey Alenin
发明人： Paul G. Damitio , Sergey Alenin
IPC分类号： H03F3/26
CPC分类号： H03F3/3432 , H03F1/02 , H03F1/42 , H03F3/3069
摘要： A high output current wideband output stage/buffer amplifier that has reduced quiescent current requirements. The output stage/buffer amplifier includes a diamond follower circuit having a pair of complementary output load-driving bipolar junction transistors (BJTs), a pair of pre-driver BJTs, and a plurality of current boost BJTs. As the base current of one of the driver transistors starts to increase in response to an increasing load current, the current through a corresponding pre-driver transistor decreases, thereby increasing the collector current of a corresponding boost transistor. The increased collector current of the boost transistor is fed back to a current mirror, causing a concomitant increase in the base current of the driver transistor.
摘要翻译：具有降低静态电流要求的高输出电流宽带输出级/缓冲放大器。输出级/缓冲放大器包括具有一对互补输出负载驱动双极结晶体管（BJT），一对预驱动器BJT和多个电流升压BJT的金刚石跟随器电路。随着一个驱动晶体管的基极电流响应于负载电流的增加而开始增加，相应的预驱动晶体管的电流减小，从而增加对应的升压晶体管的集电极电流。升压晶体管的集电极电流的增加被反馈到电流镜，引起驱动晶体管的基极电流的伴随增加。

6. 发明授权

US07626458B2 Common-mode bandwidth reduction circuit and method for differential applications 有权
标题翻译：共模带宽降低电路和差分应用的方法
公开(公告)号：US07626458B2
公开(公告)日：2009-12-01
申请号：US11903105
申请日：2007-09-20
申请人： Paul G. Damitio , Ahmad Dashtestani
发明人： Paul G. Damitio , Ahmad Dashtestani
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/45475 , H03F3/45479 , H03F3/45968 , H03F2203/45048 , H03F2203/45356 , H03F2203/45392 , H03F2203/45394 , H03F2203/45588 , H03F2203/45681 , H03F2203/45726
摘要： An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively. Lower bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (16-1) and second (16-2) lower current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (14-2) and first (14-1) upper current mirrors, respectively, to oppose signals at the inputs (IN) of the current mirrors in response to the common mode input signal.
摘要翻译：放大器驱动器电路（10）分别包括第一（11-1）和第二（11-2）个反馈放大器，分别包括第一（14-1）和第二（14-2）上电流镜，第一（16-1）和第二（16-2）个下电流镜，第一（12-1）和第二（12-2））放大器输入级接收共模输入信号，以及第一（18-1）和第二（18-2）放大器输出级分别耦合到第一和第二放大器输入级的输出。每个电流镜具有输入（IN）和第一（OUT1）和第二（OUT2）输出。第一（12-1）和第二（12-2）放大器输入级的上偏置端分别耦合到第一（14-1）和第二（14-2）上电流镜的输入（IN）并分别交叉耦合到第二（16-2）和第一（16-1）下电流镜的第二输出端（OUT2）。第一（12-1）和第二（12-2）放大器输入级的低偏置端分别耦合到第一（16-1）和第二（16-2）下电流镜的输入（IN）并且分别与第二（14-2）和第一（14-1）上电流镜的第二输出（OUT2）交叉耦合，以与当前反射镜的输入（IN）响应于相应于共模输入信号。

7. 发明授权

US07528661B2 Low quiescent current output stage and method with improved output drive 有权
标题翻译：低静态电流输出级和改进输出驱动方式
公开(公告)号：US07528661B2
公开(公告)日：2009-05-05
申请号：US11890682
申请日：2007-08-07
申请人： Paul G. Damitio
发明人： Paul G. Damitio
IPC分类号： H03F3/26
CPC分类号： H03F1/307 , H03F1/0261 , H03F3/3069 , H03F2203/30015 , H03F2203/30147 , H03F2203/30153
摘要： Circuitry for increasing the maximum output current magnitude of a diamond buffer (Q57,58,74,75) having increased maximum output current provides a bias current of a first magnitude (I) into an emitter of a PNP first input transistor (Q57) and sinks a bias current of the first magnitude out of an emitter of an NPN second input transistor (Q55). The decrease is sensed in a collector current of the first input transistor caused by a demand for increased base current by a NPN first output transistor (Q74) of the diamond buffer. A collector current (Ic(65)) in an NPN another transistor (Q65) is increased in response to the decrease in the collector current of the first input transistor. The increased collector current in the first transistor is mirrored into a base of the first output transistor to boost its base current and maintain operation of the first input transistor when the amount of base current demanded by the first output transistor exceeds the first magnitude.
摘要翻译：增加具有增加的最大输出电流的金刚石缓冲器的最大输出电流幅度（Q57,58,74,75）的电路提供第一幅度（I）到PNP第一输入晶体管（Q57）的发射极的偏置电流，并且从NPN第二输入晶体管（Q55）的发射极吸收第一幅度的偏置电流。由于由金刚石缓冲器的NPN第一输出晶体管（Q74）增加的基极电流的需求引起的，在第一输入晶体管的集电极电流中感测到该减小。响应于第一输入晶体管的集电极电流的减小，另一晶体管（Q65）中的NPN中的集电极电流（Ic（65））增加。当第一输出晶体管所需的基极电流量超过第一幅度时，第一晶体管中增加的集电极电流被镜像到第一输出晶体管的基极中，以提升其基极电流并保持第一输入晶体管的工作。

8. 发明申请

US20120146725A1 GATED CLASS H AMPLIFIER/LINE DRIVER SYSTEM AND METHOD 有权
标题翻译：门阵列放大器/线驱动系统及方法
公开(公告)号：US20120146725A1
公开(公告)日：2012-06-14
申请号：US12928468
申请日：2010-12-13
申请人： Paul G. Damitio , Xavier P. Ramus , He Qing
发明人： Paul G. Damitio , Xavier P. Ramus , He Qing
IPC分类号： H03F3/45
CPC分类号： H03F3/21 , H03F1/0222 , H03F2200/321
摘要： Amplifier circuitry (10) includes a driver amplifier (11) and an integrator amplifier (AH) producing an output signal (VAH) that controls a pass transistor (Q2) coupled to a pump capacitor (CH). Input circuitry (16) controls the direction of ramping of the output signal during a first interval to boost a supply voltage (V12) of the driver amplifier via the pump capacitor, and also controls the direction of ramping to recharge the pump capacitor following a second interval. In one embodiment, pump capacitor recharging circuitry (Q75,R76,ICHH) completes the recharging of the pump capacitor following the second interval after it has been partially recharged by the integrator amplifier.
摘要翻译：放大器电路（10）包括驱动放大器（11）和积分放大器（AH），其产生控制耦合到泵电容器（CH）的通过晶体管（Q2）的输出信号（VAH）。输入电路（16）在第一间隔期间控制输出信号的斜坡的方向，以通过泵电容器升高驱动放大器的电源电压（V12），并且还控制斜坡的方向以在第二时间之后对泵电容器再充电间隔。在一个实施例中，泵电容器充电电路（Q75，R76，ICHH）在其被积分放大器部分再充电之后，在第二间隔之后完成泵电容器的再充电。

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