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1. 发明授权

US4777470A High speed successive approximation register in analog-to-digital converter 失效
标题翻译：模数转换器中的高速逐次逼近寄存器
公开(公告)号：US4777470A
公开(公告)日：1988-10-11
申请号：US101760
申请日：1987-09-28
申请人： Jimmy R. Naylor , Joel M. Halbert , Wallace Burney
发明人： Jimmy R. Naylor , Joel M. Halbert , Wallace Burney
IPC分类号： H03M1/38 , H03M1/00 , H03M1/46
CPC分类号： H03M1/42 , H03M1/46
摘要： In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate. Beginning with the most significant bit (MSB), each successive digital approximation number applied to the DAC consists of a "1" gated to the DAC by the shift register bit presently containing the propagating "0". After the present digital approximation number has been compared (by a comparator) to the analog input current, the resulting comparator data is latched into the data latch as the "0" shifts to the next bit. When the procedure has been completed for all N bits, the N bit word stored in the N data latches accurately represents the analog input current.
摘要翻译：在逐次逼近模拟数字转换器中，逐次逼近寄存器（SAR）包括一个N位边缘触发移位寄存器，每个位包括一个主从触发器。每个移位寄存器位的输出被施加到D型锁存器的锁存器输入和执行逻辑“与”功能的双输入门的一个输入。门的另一个输入端连接到锁存器的输出端。 N个锁存器中的每一个的D输入端连接到对应的比较器的输出，该比较器响应于由N位数模转换器（DAC）产生的逐次逼近数，将模拟输入信号与由N位数模转换器（DAC）产生的信号进行比较特区门输出连接到DAC的数字输入。 A“0”以DAC转换速率传播通过移位寄存器。从最高有效位（MSB）开始，施加到DAC的每个连续的数字近似值由当前包含传播“0”的移位寄存器位选通到DAC的“1”组成。在将当前数字近似值（由比较器）与模拟输入电流进行比较之后，当“0”移位到下一位时，所得到的比较器数据被锁存到数据锁存器中。当所有N位完成程序时，存储在N个数据锁存器中的N位字准确地表示模拟输入电流。

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