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1. 发明申请

US20150145018A1 Semiconductor Devices 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150145018A1
公开(公告)日：2015-05-28
申请号：US14568737
申请日：2014-12-12
申请人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/49 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。第一浓度可能高于第二浓度。

2. 发明授权

US08232590B2 Nonvolatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08232590B2
公开(公告)日：2012-07-31
申请号：US12829689
申请日：2010-07-02
申请人： Byoungsun Ju , Sunggil Kim , Jintae Noh , Siyoung Choi , Kihyun Hwang
发明人： Byoungsun Ju , Sunggil Kim , Jintae Noh , Siyoung Choi , Kihyun Hwang
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/4916 , H01L29/66825
摘要： Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.
摘要翻译：提供了一种非易失性存储器件。非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

3. 发明授权

US09831267B2 Three-dimensional semiconductor device 有权
公开(公告)号：US09831267B2
公开(公告)日：2017-11-28
申请号：US15239434
申请日：2016-08-17
申请人： Seulye Kim , Ji-Hoon Choi , Dongkyum Kim , Jung Ho Kim , Jintae Noh , Eun-Young Lee
发明人： Seulye Kim , Ji-Hoon Choi , Dongkyum Kim , Jung Ho Kim , Jintae Noh , Eun-Young Lee
IPC分类号： H01L27/115 , H01L23/528 , H01L21/768 , H01L23/522 , H01L27/11582 , H01L27/11565
CPC分类号： H01L27/11582 , H01L21/76831 , H01L23/485 , H01L27/11565
摘要： A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.

4. 发明授权

US09799657B2 Method of manufacturing a three-dimensional semiconductor memory device 有权
公开(公告)号：US09799657B2
公开(公告)日：2017-10-24
申请号：US15302032
申请日：2014-06-23
申请人： Jintae Noh , Bio Kim , Su-Jin Shin , Hanvit Yang , Kihyun Hwang
发明人： Jintae Noh , Bio Kim , Su-Jin Shin , Hanvit Yang , Kihyun Hwang
IPC分类号： H01L21/033 , H01L27/105 , H01L21/02 , H01L21/311 , H01L29/40
CPC分类号： H01L27/1052 , H01L21/02323 , H01L21/02532 , H01L21/02595 , H01L21/0332 , H01L21/31144 , H01L21/32105 , H01L27/11582 , H01L29/401 , H01L29/7926
摘要： The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.

5. 发明授权

US08476692B2 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08476692B2
公开(公告)日：2013-07-02
申请号：US13037502
申请日：2011-03-01
申请人： Jeeyong Kim , WoonKyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , WoonKyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/778
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。第一浓度可能高于第二浓度。

6. 发明申请

US20150279857A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150279857A1
公开(公告)日：2015-10-01
申请号：US14539140
申请日：2014-11-12
申请人： Jung-Hwan KIM , Hanvit YANG , Jintae NOH , Dongchul YOO
发明人： Jung-Hwan KIM , Hanvit YANG , Jintae NOH , Dongchul YOO
IPC分类号： H01L27/115 , H01L23/00
CPC分类号： H01L27/11582
摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.
摘要翻译：本发明的概念提供半导体存储器件及其制造方法。堆叠结构和垂直通道结构设置在基板上。堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。第一垂直通道图案设置在每个垂直通道结构的下部。栅极氧化层形成在第一垂直沟道图案的侧壁上。在垂直通道结构之间的衬底中形成凹陷区域。在凹陷区域中形成缓冲氧化物层。在基板中设置氧化抑制层以包围凹部。氧化抑制层与缓冲氧化物层接触并抑制缓冲氧化物层的生长。

7. 发明申请

US20110215392A1 Semiconductor Devices and Methods of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110215392A1
公开(公告)日：2011-09-08
申请号：US13037502
申请日：2011-03-01
申请人： Jeeyong Kim , WoonKyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , WoonKyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/788 , H01L21/28 , H01L23/48 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。第一浓度可能高于第二浓度。

8. 发明申请

US20110001181A1 Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20110001181A1
公开(公告)日：2011-01-06
申请号：US12829689
申请日：2010-07-02
申请人： Byoungsun Ju , Sunggil Kim , Jintae Noh , Siyoung Choi , Kihyun Hwang
发明人： Byoungsun Ju , Sunggil Kim , Jintae Noh , Siyoung Choi , Kihyun Hwang
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L29/7883 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/4916 , H01L29/66825
摘要： Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.
摘要翻译：提供了一种非易失性存储器件。非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

9. 发明授权

US09508737B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09508737B2
公开(公告)日：2016-11-29
申请号：US14539140
申请日：2014-11-12
申请人： Jung-Hwan Kim , Hanvit Yang , Jintae Noh , Dongchul Yoo
发明人： Jung-Hwan Kim , Hanvit Yang , Jintae Noh , Dongchul Yoo
IPC分类号： H01L21/04 , H01L21/20 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582
摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.
摘要翻译：本发明的概念提供半导体存储器件及其制造方法。堆叠结构和垂直通道结构设置在基板上。堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。第一垂直通道图案设置在每个垂直通道结构的下部。栅极氧化物层形成在第一垂直沟道图案的侧壁上。在垂直通道结构之间的衬底中形成凹陷区域。在凹陷区域中形成缓冲氧化物层。在基板中设置氧化抑制层以包围凹部。氧化抑制层与缓冲氧化物层接触并抑制缓冲氧化物层的生长。

10. 发明授权

US09443863B2 Semiconductor devices 有权
公开(公告)号：US09443863B2
公开(公告)日：2016-09-13
申请号：US14819841
申请日：2015-08-06
申请人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
发明人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L29/49 , H01L27/115 , H01L23/535 , H01L29/78 , H01L21/28 , H01L23/48 , H01L29/788 , H01L29/792 , H01L21/768
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

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