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1. 发明授权

US08131985B2 Semiconductor memory device having processor reset function and reset control method thereof 有权
标题翻译：具有处理器复位功能的半导体存储器件及其复位控制方法
公开(公告)号：US08131985B2
公开(公告)日：2012-03-06
申请号：US12140428
申请日：2008-06-17
申请人： Jin-Hyoung Kwon , Han-Gu Sohn
发明人： Jin-Hyoung Kwon , Han-Gu Sohn
IPC分类号： G06F9/00 , G06F15/16 , G06F12/00 , G06F15/00 , G06F11/00
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/1075 , G11C7/22
摘要： A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.
摘要翻译：用于多处理器系统的半导体存储器件包括共享存储区域和复位信号发生器。共享存储器区域可由多处理器系统的处理器通过不同端口访问，并被分配给存储单元阵列的一部分。复位信号发生器被配置为在多处理器系统的初始引导之后的预定时间内向处理器提供复位使能信号，预定为多个处理器中的从属处理器。复位信号发生器还在经过预定时间之后向从属处理器提供复位禁止信号。

2. 发明授权

US08078838B2 Multiprocessor system having multiport semiconductor memory with processor wake-up function responsive to stored messages in an internal register 失效
标题翻译：具有多端口半导体存储器的多处理器系统，具有响应于内部寄存器中存储的消息的处理器唤醒功能
公开(公告)号：US08078838B2
公开(公告)日：2011-12-13
申请号：US12235816
申请日：2008-09-23
申请人： Jin-Hyoung Kwon , Han-Gu Sohn , Kwang-Myeong Jang
发明人： Jin-Hyoung Kwon , Han-Gu Sohn , Kwang-Myeong Jang
IPC分类号： G06F15/16
CPC分类号： G06F15/167
摘要： A multiport semiconductor memory device having a processor wake-up function and multiprocessor system, the multiprocessor system including a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first and second processors. The multiport semiconductor memory device includes a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator. The first processor is coupled to the at least one shared memory area via the first port, the second processor is coupled to the at least one shared memory area via the second port, and the wake-up signal generator is coupled to the first processor and the second processor.
摘要翻译：一种具有处理器唤醒功能和多处理器系统的多端口半导体存储器件，所述多处理器系统包括被配置为执行第一预定任务的第一处理器; 配置为执行第二预定任务的第二处理器; 以及耦合到第一和第二处理器的多端口半导体存储器件。多端口半导体存储器件包括具有至少一个共享存储区域的存储单元阵列; 耦合到所述至少一个共享存储器区域的第一端口; 耦合到所述至少一个共享存储区域的第二端口; 和唤醒信号发生器。第一处理器经由第一端口耦合到至少一个共享存储器区域，第二处理器经由第二端口耦合到至少一个共享存储器区域，并且唤醒信号发生器耦合到第一处理器，并且第二个处理器。

3. 发明申请

US20110167210A1 SEMICONDUCTOR DEVICE AND SYSTEM COMPRISING MEMORIES ACCESSIBLE THROUGH DRAM INTERFACE AND SHARED MEMORY REGION 审中-公开
标题翻译：通过DRAM接口和共享存储区可访问的存储器的半导体器件和系统
公开(公告)号：US20110167210A1
公开(公告)日：2011-07-07
申请号：US12868028
申请日：2010-08-25
申请人： Jin Hyoung KWON
发明人： Jin Hyoung KWON
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0638 , G06F3/0673
摘要： A semiconductor device comprises a nonvolatile memory device, a memory device that processes data according to a DRAM protocol, and an ASIC that converts data output from the memory device into a format compatible with a nonvolatile memory device or a hard disk and outputs the converted data to the nonvolatile memory device or the hard disk.
摘要翻译：半导体器件包括非易失性存储器件，根据DRAM协议处理数据的存储器件以及将从存储器件输出的数据转换成与非易失性存储器件或硬盘兼容的格式的ASIC，并输出转换后的数据到非易失性存储器件或硬盘。

4. 发明申请

US20110107049A1 METHOD AND APPARATUS ADAPTED TO PREVENT CODE DATA FROM BEING LOST IN SOLDER REFLOW 有权
标题翻译：适用于防止在焊接机反射中丢失代码数据的方法和装置
公开(公告)号：US20110107049A1
公开(公告)日：2011-05-05
申请号：US12847073
申请日：2010-07-30
申请人： Jin Hyoung Kwon , Hui Kwon Seo
发明人： Jin Hyoung Kwon , Hui Kwon Seo
IPC分类号： G06F12/16 , G06F12/02
CPC分类号： G06F11/004 , G11C11/5628
摘要： A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted.
摘要翻译：半导体器件包括被配置为存储程序代码的第一非易失性存储器和配置成在焊料回流处理之后将程序代码从第一非易失性存储器复制到第二非易失性存储器的处理器。在处理器完全引导之后，处理器通常将程序代码从第一非易失性存储器复制到第二非易失性存储器。

5. 发明申请

US20110035575A1 MULTIPROCESSOR SYSTEM COMPRISING MULTI-PORT SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：包含多端口半导体存储器件的多处理器系统
公开(公告)号：US20110035575A1
公开(公告)日：2011-02-10
申请号：US12780989
申请日：2010-05-17
申请人： Jin-Hyoung KWON
发明人： Jin-Hyoung KWON
IPC分类号： G06F12/02 , G06F9/24 , G06F15/76 , G06F9/02
CPC分类号： G06F15/167 , G06F9/4405
摘要： A multiprocessor system comprises first and second processors connected to a multi-port semiconductor memory device. The multi-port semiconductor memory device comprises a shared memory area and a plurality of mailbox areas used for inter-processor communication. The first and second processors use a single nonvolatile memory device for storing boot data and transmit information for booting via the shared memory area.
摘要翻译：多处理器系统包括连接到多端口半导体存储器件的第一和第二处理器。多端口半导体存储器件包括共享存储器区域和用于处理器间通信的多个邮箱区域。第一和第二处理器使用单个非易失性存储器装置来存储引导数据并且通过共享存储器区域发送用于引导的信息。

6. 发明申请

US20100318725A1 Multi-Processor System Having Function of Preventing Data Loss During Power-Off in Memory Link Architecture 审中-公开
标题翻译：具有防止在内存链路架构断电期间的数据丢失功能的多处理器系统
公开(公告)号：US20100318725A1
公开(公告)日：2010-12-16
申请号：US12689854
申请日：2010-01-19
申请人： Jin-Hyoung Kwon
发明人： Jin-Hyoung Kwon
IPC分类号： G06F12/02 , G06F1/32
CPC分类号： G06F11/1441
摘要： Exemplary embodiments relate to a multi-processor system including: a first processor for writing a power-off check command to a first mail box, reading a power-off wait message or a power-off allowance message written to a second mail box, and waiting or turning off the multi-processor system, in a power-off operation mode; a second processor for indicating whether data is completely stored during a current processing operation in response to the power-off check command in the first mail box and writing the power-off wait message or the power-off allowance message to the second mail box according to the indication result; and a multi-port semiconductor memory device having an internal register that includes the first and second mail boxes and dedicated and shared memory areas for data processing. The first and second mail boxes serve as latch storage units, and the dedicated and shared memory areas are accessed by the first and second processors.
摘要翻译：示例性实施例涉及多处理器系统，包括：第一处理器，用于向第一邮箱写入断电检查命令，读取断电等待消息或写入第二邮箱的断电许可消息;以及在关机操作模式下等待或关闭多处理器系统; 第二处理器，用于响应于第一邮箱中的断电检查命令，指示在当前处理操作期间是否完全存储数据，并根据第二邮箱将关机等待消息或断电允许消息写入第二邮箱指示结果; 以及具有内部寄存器的多端口半导体存储器件，该寄存器包括第一和第二邮箱以及用于数据处理的专用和共享存储区域。第一和第二邮箱用作锁存器存储单元，并且专用和共享存储器区域被第一和第二处理器访问。

7. 发明申请

US20100287424A1 Method of writing an operating systems (OS) image to a semiconductor device and the semiconductor device 审中-公开
标题翻译：将操作系统（OS）图像写入半导体器件和半导体器件的方法
公开(公告)号：US20100287424A1
公开(公告)日：2010-11-11
申请号：US12662749
申请日：2010-05-03
申请人： Jin Hyoung Kwon
发明人： Jin Hyoung Kwon
IPC分类号： G06F12/00 , G06F9/24 , G06F11/26 , G06F12/08
CPC分类号： G06F9/4401
摘要： Example embodiments are directed to a method of writing an Operating System (OS) image to a semiconductor device having a data storage device, an Application Specific Integrated Circuit (ASIC), and a non-volatile memory. The method includes initializing a DRAM interface of the ASIC using a boot loader, receiving the OS image input from a data writer to the semiconductor device through the DRAM interface; and writing the OS image into the non-volatile memory of the semiconductor device using a Flash Translation Layer (FTL) code.
摘要翻译：示例性实施例涉及将操作系统（OS）图像写入具有数据存储设备，专用集成电路（ASIC）和非易失性存储器的半导体器件的方法。该方法包括使用引导加载程序初始化ASIC的DRAM接口，通过DRAM接口接收从数据写入器输入到半导体器件的OS映像; 并使用闪存转换层（FTL）代码将OS映像写入半导体器件的非易失性存储器。

8. 发明申请

US20090210691A1 Memory System and Memory Management Method Including the Same 有权
标题翻译：内存系统和内存管理方法包括它
公开(公告)号：US20090210691A1
公开(公告)日：2009-08-20
申请号：US12430722
申请日：2009-04-27
申请人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
发明人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
IPC分类号： G06F15/177
CPC分类号： G06F12/0607 , G06F9/4405 , G06F9/445 , G06F12/0638 , G06F15/177 , G06F2212/2022 , G11C8/16
摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.
摘要翻译：提供了具有第一处理器和第二处理器的数字处理的启动方法。第一处理器和外部之间的接口被停止。第二处理器程序代码从第一存储器发送到第二存储器。用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

9. 发明申请

US20080320204A1 MEMORY SYSTEM AND METHOD WITH FLASH MEMORY DEVICE 有权
标题翻译：具有闪存存储器件的存储器系统和方法
公开(公告)号：US20080320204A1
公开(公告)日：2008-12-25
申请号：US12144221
申请日：2008-06-23
申请人： Sung-Kyu Jo , Jin-Hyoung Kwon
发明人： Sung-Kyu Jo , Jin-Hyoung Kwon
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory.
摘要翻译：提供了一种存储器系统，其包括主机，闪存设备和与主机和闪存设备交换数据的双端口存储器。闪存器件利用双端口存储器的一部分作为工作存储器。

10. 发明授权

US08788741B2 Method and apparatus adapted to prevent code data from being lost in solder reflow 有权
标题翻译：适于防止代码数据在焊料回流中丢失的方法和装置
公开(公告)号：US08788741B2
公开(公告)日：2014-07-22
申请号：US12847073
申请日：2010-07-30
申请人： Jin Hyoung Kwon , Hui Kwon Seo
发明人： Jin Hyoung Kwon , Hui Kwon Seo
IPC分类号： G06F12/00 , G06F11/00 , G11C11/56
CPC分类号： G06F11/004 , G11C11/5628
摘要： A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted.
摘要翻译：半导体器件包括被配置为存储程序代码的第一非易失性存储器和配置成在焊料回流处理之后将程序代码从第一非易失性存储器复制到第二非易失性存储器的处理器。在处理器完全引导之后，处理器通常将程序代码从第一非易失性存储器复制到第二非易失性存储器。

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