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1. 发明授权

US08209527B2 Memory system and memory management method including the same 有权
标题翻译：内存系统和内存管理方法包括相同
公开(公告)号：US08209527B2
公开(公告)日：2012-06-26
申请号：US12430722
申请日：2009-04-27
申请人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
发明人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
IPC分类号： G06F15/177
CPC分类号： G06F12/0607 , G06F9/4405 , G06F9/445 , G06F12/0638 , G06F15/177 , G06F2212/2022 , G11C8/16
摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.
摘要翻译：提供了具有第一处理器和第二处理器的数字处理的启动方法。第一处理器和外部之间的接口被停止。第二处理器程序代码从第一存储器发送到第二存储器。用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

2. 发明授权

US08032695B2 Multi-path accessible semiconductor memory device with prevention of pre-charge skip 失效
标题翻译：具有防止预充电跳跃的多路径可访问半导体存储器件
公开(公告)号：US08032695B2
公开(公告)日：2011-10-04
申请号：US12151946
申请日：2008-05-09
申请人： Jin-Hyoung Kwon , Han-Gu Sohn , Dong-Woo Lee
发明人： Jin-Hyoung Kwon , Han-Gu Sohn , Dong-Woo Lee
IPC分类号： G06F12/16 , G06F12/00
CPC分类号： G06F13/1663 , G11C7/1075 , G11C11/4094
摘要： A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.
摘要翻译：多处理器系统包括第一和第二处理器以及包括共享存储器区域和伪操作执行单元的多路径可访问半导体存储器件。根据页面打开策略，共享存储器区域可由第一和第二处理器访问。伪操作执行单元响应来自第一和第二处理器之一的虚拟活动命令以关闭最后打开的页面。生成虚拟活动命令，其中行地址不对应于共享存储器区域的任何行。例如，最后访问的行的位线是预先关闭最后打开的页面的。

3. 发明申请

US20090019237A1 MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING CONTINUOUS ADDRESS MAP AND METHOD OF PROVIDING THE SAME 审中-公开
标题翻译：具有连续地址映射的多路可及半导体存储器件及其提供方法
公开(公告)号：US20090019237A1
公开(公告)日：2009-01-15
申请号：US12139622
申请日：2008-06-16
申请人： Jin-Hyoung Kwon , Han-Gu Sohn
发明人： Jin-Hyoung Kwon , Han-Gu Sohn
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F15/167
摘要： A semiconductor memory device for use in a multiprocessor system includes at least two shared memory areas and a row decoder. The at least two shared memory areas are accessible in common by multiple processors of the multiprocessor system through different ports, and assigned based on predetermined memory capacity to a portion of a memory cell array. The row decoder is configured to form a continuous address map for remaining memory portions of the at least two shared memory areas to be dedicated to one port. Each remaining memory portion does not include a corresponding data transfer portion within each shared memory area.
摘要翻译：一种用于多处理器系统的半导体存储器件包括至少两个共享存储区域和行解码器。所述至少两个共享存储器区域可由多处理器系统的多个处理器通过不同端口共同访问，并且基于预定的存储器容量被分配给存储器单元阵列的一部分。行解码器被配置为形成用于要专用于一个端口的至少两个共享存储器区域的剩余存储器部分的连续地址映射。每个剩余存储器部分不包括每个共享存储器区域内的对应的数据传送部分。

4. 发明申请

US20090024803A1 Multipath accessible semiconductor memory device having shared register and method of operating thereof 审中-公开
标题翻译：具有共享寄存器的多路径可访问半导体存储器件及其操作方法
公开(公告)号：US20090024803A1
公开(公告)日：2009-01-22
申请号：US12216188
申请日：2008-07-01
申请人： Jin-Hyoung Kwon , Han-Gu Sohn
发明人： Jin-Hyoung Kwon , Han-Gu Sohn
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0638 , G06F2212/206
摘要： A semiconductor memory device for use in a multiprocessor system may be provided. A chip size may be controlled, and a design of circuit may be relatively simplified. The semiconductor memory device for use in a multiprocessor system may include at least two shared memory areas commonly accessible by processors of the multiprocessor system through different ports and assigned with a predetermined memory capacity unit to a portion of a memory cell array, a single shared register adapted outside the memory cell array, corresponding to disable areas formed within the shared memory areas, and/or a switching unit for connecting a decoder of a selected shared memory area to the shared register in response to an applied control signal, to match the shared register to the disable area of the selected shared memory area. A shared register may be commonly used in corresponding to a plurality of shared memory areas, thereby reducing or preventing a chip size increase and simplifying a design of the circuit.
摘要翻译：可以提供用于多处理器系统的半导体存储器件。可以控制芯片尺寸，并且可以相对简化电路的设计。在多处理器系统中使用的半导体存储器件可以包括通过不同端口通常可由多处理器系统的处理器访问的至少两个共享存储器区域，并且向存储器单元阵列的一部分分配预定的存储器容量单元，单个共享寄存器对应于形成在共享存储器区域内的禁用区域，和/或用于响应于所施加的控制信号将所选择的共享存储器区域的解码器连接到共享寄存器的切换单元，以匹配共享存储器单元阵列注册到所选共享内存区域的禁用区域。可以在多个共享存储区域中共同使用共享寄存器，从而减少或防止芯片尺寸增加并简化电路的设计。

5. 发明申请

US20080313418A1 SEMICONDUCTOR MEMORY DEVICE HAVING PROCESSOR RESET FUNCTION AND RESET CONTROL METHOD THEREOF 有权
标题翻译：具有处理器复位功能的半导体存储器件及其复位控制方法
公开(公告)号：US20080313418A1
公开(公告)日：2008-12-18
申请号：US12140428
申请日：2008-06-17
申请人： Jin-Hyoung KWON , Han-Gu Sohn
发明人： Jin-Hyoung KWON , Han-Gu Sohn
IPC分类号： G06F12/00
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/1075 , G11C7/22
摘要： A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.
摘要翻译：用于多处理器系统的半导体存储器件包括共享存储区域和复位信号发生器。共享存储器区域可由多处理器系统的处理器通过不同端口访问，并被分配给存储单元阵列的一部分。复位信号发生器被配置为在多处理器系统的初始引导之后的预定时间内向处理器提供复位使能信号，预定为多个处理器中的从属处理器。复位信号发生器还在经过预定时间之后向从属处理器提供复位禁止信号。

6. 发明授权

US08171279B2 Multi processor system having direct access boot and direct access boot method thereof 有权
标题翻译：具有直接访问引导和直接访问引导方法的多处理器系统
公开(公告)号：US08171279B2
公开(公告)日：2012-05-01
申请号：US12211183
申请日：2008-09-16
申请人： Jin-Hyoung Kwon , Han-Gu Sohn
发明人： Jin-Hyoung Kwon , Han-Gu Sohn
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F15/16 , G06F9/4405
摘要： A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise.
摘要翻译：提供具有直接访问引导操作和直接访问引导方法的多处理器系统，以显着减少在多处理器系统中不提供存储器链接体系结构的处理器的引导错误。在本发明的一个实施例中，多处理器系统包括：第一处理器，被配置为执行第一预定任务; 配置为执行第二预定任务的第二处理器; 耦合到所述第一处理器和所述第二处理器的多端口半导体存储器件，所述多端口半导体存储器件包括至少一个共享存储器区域，所述多端口半导体存储器件被配置为提供由所述第一处理器访问所述至少一个共享存储器区域;以及第二处理器; 以及耦合到所述第一处理器和所述第二处理器的所述非易失性存储器设备，所述非易失性存储器设备存储与所述第一处理器相关联的第一引导代码和与所述第二处理器相关联的第二引导代码，所述多处理器系统被配置为提供第一处理器在引导操作期间直接访问非易失性存储器区域，而间接访问非易失性存储器区域。

7. 发明授权

US08122199B2 Multi port memory device with shared memory area using latch type memory cells and driving method 失效
标题翻译：具有共享存储区域的多端口存储器件使用锁存型存储单元和驱动方法
公开(公告)号：US08122199B2
公开(公告)日：2012-02-21
申请号：US12392432
申请日：2009-02-25
申请人： Jin-Hyoung Kwon , Kyung-Woo Nam , Han-Gu Sohn , Ho-Cheol Lee , Kwang-Myeong Jang
发明人： Jin-Hyoung Kwon , Kyung-Woo Nam , Han-Gu Sohn , Ho-Cheol Lee , Kwang-Myeong Jang
IPC分类号： G06F12/00
CPC分类号： G11C11/413 , G11C7/1075
摘要： A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.
摘要翻译：多端口半导体存储器件包括：分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一和第二个处理器通过共享内存区域。

8. 发明申请

US20080282042A1 Multi-path accessible semiconductor memory device with prevention of pre-charge skip 失效
标题翻译：具有防止预充电跳跃的多路径可访问半导体存储器件
公开(公告)号：US20080282042A1
公开(公告)日：2008-11-13
申请号：US12151946
申请日：2008-05-09
申请人： Jin-Hyoung Kwon , Han-Gu Sohn , Dong-Woo Lee
发明人： Jin-Hyoung Kwon , Han-Gu Sohn , Dong-Woo Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G11C7/1075 , G11C11/4094
摘要： A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.
摘要翻译：多处理器系统包括第一和第二处理器以及包括共享存储器区域和伪操作执行单元的多路径可访问半导体存储器件。根据页面打开策略，共享存储器区域可由第一和第二处理器访问。伪操作执行单元响应来自第一和第二处理器之一的虚拟活动命令以关闭最后打开的页面。生成虚拟活动命令，其中行地址不对应于共享存储器区域的任何行。例如，最后访问的行的位线是预先关闭最后打开的页面的。

9. 发明授权

US08131985B2 Semiconductor memory device having processor reset function and reset control method thereof 有权
标题翻译：具有处理器复位功能的半导体存储器件及其复位控制方法
公开(公告)号：US08131985B2
公开(公告)日：2012-03-06
申请号：US12140428
申请日：2008-06-17
申请人： Jin-Hyoung Kwon , Han-Gu Sohn
发明人： Jin-Hyoung Kwon , Han-Gu Sohn
IPC分类号： G06F9/00 , G06F15/16 , G06F12/00 , G06F15/00 , G06F11/00
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/1075 , G11C7/22
摘要： A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.
摘要翻译：用于多处理器系统的半导体存储器件包括共享存储区域和复位信号发生器。共享存储器区域可由多处理器系统的处理器通过不同端口访问，并被分配给存储单元阵列的一部分。复位信号发生器被配置为在多处理器系统的初始引导之后的预定时间内向处理器提供复位使能信号，预定为多个处理器中的从属处理器。复位信号发生器还在经过预定时间之后向从属处理器提供复位禁止信号。

10. 发明授权

US08078838B2 Multiprocessor system having multiport semiconductor memory with processor wake-up function responsive to stored messages in an internal register 失效
标题翻译：具有多端口半导体存储器的多处理器系统，具有响应于内部寄存器中存储的消息的处理器唤醒功能
公开(公告)号：US08078838B2
公开(公告)日：2011-12-13
申请号：US12235816
申请日：2008-09-23
申请人： Jin-Hyoung Kwon , Han-Gu Sohn , Kwang-Myeong Jang
发明人： Jin-Hyoung Kwon , Han-Gu Sohn , Kwang-Myeong Jang
IPC分类号： G06F15/16
CPC分类号： G06F15/167
摘要： A multiport semiconductor memory device having a processor wake-up function and multiprocessor system, the multiprocessor system including a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first and second processors. The multiport semiconductor memory device includes a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator. The first processor is coupled to the at least one shared memory area via the first port, the second processor is coupled to the at least one shared memory area via the second port, and the wake-up signal generator is coupled to the first processor and the second processor.
摘要翻译：一种具有处理器唤醒功能和多处理器系统的多端口半导体存储器件，所述多处理器系统包括被配置为执行第一预定任务的第一处理器; 配置为执行第二预定任务的第二处理器; 以及耦合到第一和第二处理器的多端口半导体存储器件。多端口半导体存储器件包括具有至少一个共享存储区域的存储单元阵列; 耦合到所述至少一个共享存储器区域的第一端口; 耦合到所述至少一个共享存储区域的第二端口; 和唤醒信号发生器。第一处理器经由第一端口耦合到至少一个共享存储器区域，第二处理器经由第二端口耦合到至少一个共享存储器区域，并且唤醒信号发生器耦合到第一处理器，并且第二个处理器。

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