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1. 发明授权

US08836038B2 CMOS dual metal gate semiconductor device 有权
标题翻译： CMOS双金属栅极半导体器件
公开(公告)号：US08836038B2
公开(公告)日：2014-09-16
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

2. 发明授权

US08384159B2 Semiconductor devices and methods with bilayer dielectrics 有权
标题翻译：具有双层电介质的半导体器件和方法
公开(公告)号：US08384159B2
公开(公告)日：2013-02-26
申请号：US12426477
申请日：2009-04-20
申请人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.
摘要翻译：公开了一种半导体器件，包括：衬底; 形成在所述衬底上并由第一高k材料形成的第一介电层，所述第一高k材料选自HfO 2，HfSiO，HfSiON，HfTaO，HfTiO，HfTiTaO，HfAlON和HfZrO; 形成在所述第一介电层上并由第二高k材料形成的第二介电层，所述第二高k材料不同于所述第一高k材料并选自HfO 2，HfSiO，HfSiON，HfTaO， HfTiO，HfTiTaO，HfAlON和HfZrO; 以及形成在第二介电层上的金属栅极。第一电介质层包括选自N，O和Si的离子。

3. 发明授权

US07939396B2 Base oxide engineering for high-K gate stacks 有权
标题翻译：高K栅极堆叠的基础氧化物工程
公开(公告)号：US07939396B2
公开(公告)日：2011-05-10
申请号：US11450204
申请日：2006-06-09
申请人： Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/02312 , H01L21/02046 , H01L21/02181 , H01L21/02194 , H01L21/02238 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/3141 , H01L21/31641 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.
摘要翻译：形成半导体结构的方法包括提供半导体衬底，对半导体衬底进行氢退火，在氢退火步骤之后形成基底氧化物层，以及在基底氧化物层上形成高k电介质层。

4. 发明申请

US20080096336A1 Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures 有权
标题翻译：形成具有n-MOSFET和p-MOSFET晶体管的集成电路器件的方法，其具有升高和硅化源极/漏极结构
公开(公告)号：US20080096336A1
公开(公告)日：2008-04-24
申请号：US11583500
申请日：2006-10-18
申请人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/337
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.
摘要翻译： n-FET和p-FET各自具有升高的源极/漏极结构。可选地，p-FET升高的SOURCE / DRAIN结构从形成在衬底中的p-FET凹槽外延生长。可选地，n-FET升高的SOURCE / DRAIN结构从形成在衬底中的n-FET凹槽外延生长。即使结构可能具有不同的材料和/或不同的结构高度，n-FET和p-FET升高源极/漏极结构都是硅化的。对于n-FET和p-FET升高的源极/漏极结构，至少对源极/漏极结构硅化物的热处理部分同时进行。此外，p-FET栅电极，n-FET栅电极或两者可以可选地与n-FET和p-FET升高源极/漏极结构同时（相同的金属和/或相同的热处理步骤）硅化，分别; 即使栅电极可以具有不同的材料，不同的硅化物金属和/或不同的电极高度。在n-FET和p-FET升高源极/漏极结构上形成的硅化物优选不超过约250埃延伸到衬底的顶表面下方; 并且可以选择结构高度来提供这一点。

5. 发明申请

US20070287199A1 Base oxide engineering for high-K gate stacks 有权
标题翻译：高K栅极堆叠的基础氧化物工程
公开(公告)号：US20070287199A1
公开(公告)日：2007-12-13
申请号：US11450204
申请日：2006-06-09
申请人： Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/02312 , H01L21/02046 , H01L21/02181 , H01L21/02194 , H01L21/02238 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/3141 , H01L21/31641 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.
摘要翻译：形成半导体结构的方法包括提供半导体衬底，对半导体衬底进行氢退火，在氢退火步骤之后形成基底氧化物层，以及在基底氧化物层上形成高k电介质层。

6. 发明授权

US07824990B2 Multi-metal-oxide high-K gate dielectrics 有权
标题翻译：多金属氧化物高K栅极电介质
公开(公告)号：US07824990B2
公开(公告)日：2010-11-02
申请号：US11328933
申请日：2006-01-10
申请人： Vincent S. Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
发明人： Vincent S. Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L21/02175 , H01L21/0228 , H01L21/02337 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/1054 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
摘要翻译：提供具有高k电介质的半导体结构及其制造方法。一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。所有氧化金属的原子比在非晶高k电介质层内基本均匀。

7. 发明申请

US20090315125A1 SEMICONDUCTOR DEVICES AND METHODS WITH BILAYER DIELECTRICS 有权
标题翻译：半导体器件和方法与双极电介质
公开(公告)号：US20090315125A1
公开(公告)日：2009-12-24
申请号：US12426477
申请日：2009-04-20
申请人： Fong-Yu YEN , Cheng-Lung HUNG , Peng-Fu HSU , Vencent S. CHANG , Yong-Tian HOU , Jin YING , Hun-Jan TAO
发明人： Fong-Yu YEN , Cheng-Lung HUNG , Peng-Fu HSU , Vencent S. CHANG , Yong-Tian HOU , Jin YING , Hun-Jan TAO
IPC分类号： H01L29/78
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.
摘要翻译：公开了一种半导体器件，包括：衬底; 形成在所述衬底上并由第一高k材料形成的第一介电层，所述第一高k材料选自HfO 2，HfSiO，HfSiON，HfTaO，HfTiO，HfTiTaO，HfAlON和HfZrO; 形成在所述第一介电层上并由第二高k材料形成的第二介电层，所述第二高k材料不同于所述第一高k材料并选自HfO 2，HfSiO，HfSiON，HfTaO， HfTiO，HfTiTaO，HfAlON和HfZrO; 以及形成在第二介电层上的金属栅极。第一电介质层包括选自N，O和Si的离子。

8. 发明申请

US20080093682A1 Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices 审中-公开
标题翻译：硅栅结构的多晶硅层，包括MOSFET栅电极和3D器件
公开(公告)号：US20080093682A1
公开(公告)日：2008-04-24
申请号：US11583491
申请日：2006-10-18
申请人： Liang-Gi Yao , Jin Ying , Hun-Jan Tao , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Jin Ying , Hun-Jan Tao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L29/76
CPC分类号： H01L21/823443 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7833
摘要： Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.
摘要翻译：提供了具有硅化物栅电极和制造方法的半导体结构。一种器件包括形成在第一有源区中的第一硅化结构和形成在第二有源区中的第二硅化结构。两个硅化物结构具有不同的金属浓度。形成硅化器件的方法包括在第一和第二器件制造区域上形成多晶硅结构。实施例包括用金属替代第一器件制造区上的多晶硅结构的第一部分，并用金属代替第二器件制造区上的多晶硅结构的第二部分。优选地，第二部分不同于第一部分。实施例还包括使第一和第二器件制造区上的多晶硅结构与金属反应以形成硅化物。

9. 发明申请

US20080070395A1 SEMICONDUCTOR DEVICES AND METHODS WITH BILAYER DIELECTRICS 有权
标题翻译：半导体器件和方法与双极电介质
公开(公告)号：US20080070395A1
公开(公告)日：2008-03-20
申请号：US11532308
申请日：2006-09-15
申请人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/3205 , H01L29/78 , H01L29/792
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.
摘要翻译：公开了一种半导体器件，包括：衬底; 第一高k电介质层; 由不同的高k材料形成的第二高k电介质层; 和金属门。在另一种形式中，公开了一种形成半导体器件的方法，包括：提供衬底; 在所述衬底上形成第一高k电介质层; 在所述第一介电层上形成不同高k材料的第二电介质层; 以及在所述第二电介质层上形成栅极结构。在另一种形式中，公开了一种形成半导体器件的方法，其包括：提供衬底; 在基底上形成界面层; 在界面层上形成第一高k电介质层; 进行氮化技术; 进行退火; 在所述第一介电层上形成不同高k材料的第二高k电介质层; 以及在所述第二电介质层上方形成金属栅极结构。

10. 发明申请

US20070128736A1 Multi-metal-oxide high-k gate dielectrics 有权
标题翻译：多金属氧化物高k栅极电介质
公开(公告)号：US20070128736A1
公开(公告)日：2007-06-07
申请号：US11328933
申请日：2006-01-10
申请人： Vincent Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
发明人： Vincent Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/02175 , H01L21/0228 , H01L21/02337 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/1054 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
摘要翻译：提供具有高k电介质的半导体结构及其制造方法。一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。所有氧化金属的原子比在非晶高k电介质层内基本均匀。

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