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1. 发明申请

US20070128736A1 Multi-metal-oxide high-k gate dielectrics 有权
标题翻译：多金属氧化物高k栅极电介质
公开(公告)号：US20070128736A1
公开(公告)日：2007-06-07
申请号：US11328933
申请日：2006-01-10
申请人： Vincent Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
发明人： Vincent Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/02175 , H01L21/0228 , H01L21/02337 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/1054 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
摘要翻译：提供具有高k电介质的半导体结构及其制造方法。一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。所有氧化金属的原子比在非晶高k电介质层内基本均匀。

2. 发明授权

US07824990B2 Multi-metal-oxide high-K gate dielectrics 有权
标题翻译：多金属氧化物高K栅极电介质
公开(公告)号：US07824990B2
公开(公告)日：2010-11-02
申请号：US11328933
申请日：2006-01-10
申请人： Vincent S. Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
发明人： Vincent S. Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L21/02175 , H01L21/0228 , H01L21/02337 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/1054 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
摘要翻译：提供具有高k电介质的半导体结构及其制造方法。一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。所有氧化金属的原子比在非晶高k电介质层内基本均匀。

3. 发明申请

US20080096336A1 Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures 有权
标题翻译：形成具有n-MOSFET和p-MOSFET晶体管的集成电路器件的方法，其具有升高和硅化源极/漏极结构
公开(公告)号：US20080096336A1
公开(公告)日：2008-04-24
申请号：US11583500
申请日：2006-10-18
申请人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/337
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.
摘要翻译： n-FET和p-FET各自具有升高的源极/漏极结构。可选地，p-FET升高的SOURCE / DRAIN结构从形成在衬底中的p-FET凹槽外延生长。可选地，n-FET升高的SOURCE / DRAIN结构从形成在衬底中的n-FET凹槽外延生长。即使结构可能具有不同的材料和/或不同的结构高度，n-FET和p-FET升高源极/漏极结构都是硅化的。对于n-FET和p-FET升高的源极/漏极结构，至少对源极/漏极结构硅化物的热处理部分同时进行。此外，p-FET栅电极，n-FET栅电极或两者可以可选地与n-FET和p-FET升高源极/漏极结构同时（相同的金属和/或相同的热处理步骤）硅化，分别; 即使栅电极可以具有不同的材料，不同的硅化物金属和/或不同的电极高度。在n-FET和p-FET升高源极/漏极结构上形成的硅化物优选不超过约250埃延伸到衬底的顶表面下方; 并且可以选择结构高度来提供这一点。

4. 发明授权

US07465634B2 Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures 有权
公开(公告)号：US07465634B2
公开(公告)日：2008-12-16
申请号：US11583500
申请日：2006-10-18
申请人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

5. 发明申请

US20080070395A1 SEMICONDUCTOR DEVICES AND METHODS WITH BILAYER DIELECTRICS 有权
标题翻译：半导体器件和方法与双极电介质
公开(公告)号：US20080070395A1
公开(公告)日：2008-03-20
申请号：US11532308
申请日：2006-09-15
申请人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/3205 , H01L29/78 , H01L29/792
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.
摘要翻译：公开了一种半导体器件，包括：衬底; 第一高k电介质层; 由不同的高k材料形成的第二高k电介质层; 和金属门。在另一种形式中，公开了一种形成半导体器件的方法，包括：提供衬底; 在所述衬底上形成第一高k电介质层; 在所述第一介电层上形成不同高k材料的第二电介质层; 以及在所述第二电介质层上形成栅极结构。在另一种形式中，公开了一种形成半导体器件的方法，其包括：提供衬底; 在基底上形成界面层; 在界面层上形成第一高k电介质层; 进行氮化技术; 进行退火; 在所述第一介电层上形成不同高k材料的第二高k电介质层; 以及在所述第二电介质层上方形成金属栅极结构。

6. 发明授权

US07531399B2 Semiconductor devices and methods with bilayer dielectrics 有权
标题翻译：具有双层电介质的半导体器件和方法
公开(公告)号：US07531399B2
公开(公告)日：2009-05-12
申请号：US11532308
申请日：2006-09-15
申请人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.
摘要翻译：公开了一种半导体器件，包括：衬底; 第一高k电介质层; 由不同的高k材料形成的第二高k电介质层; 和金属门。在另一种形式中，公开了一种形成半导体器件的方法，包括：提供衬底; 在所述衬底上形成第一高k电介质层; 在所述第一介电层上形成不同高k材料的第二电介质层; 以及在所述第二电介质层上形成栅极结构。在另一种形式中，公开了一种形成半导体器件的方法，其包括：提供衬底; 在基底上形成界面层; 在界面层上形成第一高k电介质层; 进行氮化技术; 进行退火; 在所述第一介电层上形成不同高k材料的第二高k电介质层; 以及在所述第二电介质层上方形成金属栅极结构。

7. 发明申请

US20080001237A1 Semiconductor device having nitrided high-k gate dielectric and metal gate electrode and methods of forming same 审中-公开
标题翻译：具有氮化高k栅极电介质和金属栅电极的半导体器件及其形成方法
公开(公告)号：US20080001237A1
公开(公告)日：2008-01-03
申请号：US11478476
申请日：2006-06-29
申请人： Vincent S. Chang , Peng-Fu Hsu , Fong-Yu Yen , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Vincent S. Chang , Peng-Fu Hsu , Fong-Yu Yen , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/78
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/823437 , H01L21/823462 , H01L21/823475 , H01L21/823828 , H01L21/823857 , H01L21/823871 , H01L29/4966 , H01L29/518 , H01L29/7833
摘要： Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.
摘要翻译：公开了一种半导体器件，其具有基板，在所述基板上形成的界面层，在所述界面层上形成的含氮高介电常数（高k）层和所述含氮高k层上的金属电极。还公开了一种形成晶体管的方法，包括在衬底上形成包含硅和氧的界面层，在界面层上沉积高k电介质材料，氮化高k电介质材料，在高介电材料上沉积金属层， k电介质材料，并且图案化金属层，高k电介质材料和界面层以形成栅极堆叠。

8. 发明授权

US08384159B2 Semiconductor devices and methods with bilayer dielectrics 有权
标题翻译：具有双层电介质的半导体器件和方法
公开(公告)号：US08384159B2
公开(公告)日：2013-02-26
申请号：US12426477
申请日：2009-04-20
申请人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.
摘要翻译：公开了一种半导体器件，包括：衬底; 形成在所述衬底上并由第一高k材料形成的第一介电层，所述第一高k材料选自HfO 2，HfSiO，HfSiON，HfTaO，HfTiO，HfTiTaO，HfAlON和HfZrO; 形成在所述第一介电层上并由第二高k材料形成的第二介电层，所述第二高k材料不同于所述第一高k材料并选自HfO 2，HfSiO，HfSiON，HfTaO， HfTiO，HfTiTaO，HfAlON和HfZrO; 以及形成在第二介电层上的金属栅极。第一电介质层包括选自N，O和Si的离子。

9. 发明申请

US20080242108A1 Method for fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080242108A1
公开(公告)日：2008-10-02
申请号：US11730551
申请日：2007-04-02
申请人： Weng Chang , Fong-Yu Yen , Hun-Jan Tao , Mong-Song Liang
发明人： Weng Chang , Fong-Yu Yen , Hun-Jan Tao , Mong-Song Liang
IPC分类号： H01L21/46
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/67207
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供第一室和第二室。第一室和第二室通过压力差单元连接，用于在第一室中的基板上沉积金属膜，经由压差单元将衬底转移到第二室，而不将衬底暴露于周围环境;以及在第二室中的金属膜上沉积含硅膜。

10. 发明授权

US07378713B2 Semiconductor devices with dual-metal gate structures and fabrication methods thereof 有权
标题翻译：具有双金属栅极结构的半导体器件及其制造方法
公开(公告)号：US07378713B2
公开(公告)日：2008-05-27
申请号：US11552704
申请日：2006-10-25
申请人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
发明人： Peng-Fu Hsu , Fong-Yu Yen , Yi-Shien Mor , Huan-Just Lin , Ying Jin , Hun-Jan Tao
IPC分类号： H01L27/092 , H01L29/423
CPC分类号： H01L21/823842 , H01L21/28088 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
摘要翻译：具有双金属栅极结构的半导体器件及其制造方法。提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层插入层和第二金属层上的多晶硅层。第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

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