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1. 发明授权

US09152418B2 Apparatus and method of exception handling for reconfigurable architecture 有权
标题翻译：可重构架构异常处理的装置和方法
公开(公告)号：US09152418B2
公开(公告)日：2015-10-06
申请号：US11487407
申请日：2006-07-17
申请人： Hee Seok Kim , Dong-Hoon Yoo , Jeong Wook Kim , Soo Jung Ryu
发明人： Hee Seok Kim , Dong-Hoon Yoo , Jeong Wook Kim , Soo Jung Ryu
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/30105 , G06F9/30116 , G06F9/30123 , G06F9/3863
摘要： A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.
摘要翻译：一种处理器，包括包括多个处理元件的粗粒子阵列，包括第一多个寄存器文件的中央寄存器文件，包括第二多个寄存器文件的影子中心寄存器文件，与每个寄存器文件相对应的第二多个寄存器堆中的每一个包括在中央寄存器文件中的第一多个寄存器文件和多个影子寄存器文件，多个影子寄存器文件中的每一个对应于包括在从多个寄存器文件中选择的预定处理元件中的第三多个寄存器文件中的每一个处理元件。

2. 发明授权

US08645955B2 Multitasking method and apparatus for reconfigurable array 有权
标题翻译：用于可重构阵列的多任务方法和装置
公开(公告)号：US08645955B2
公开(公告)日：2014-02-04
申请号：US11808750
申请日：2007-06-12
申请人： Keun-soo Yim , Jeong-joon Yoo , Jeong-wook Kim , Soo-jung Ryu , Jung-keun Park , Jae-don Lee , Young-sam Shin
发明人： Keun-soo Yim , Jeong-joon Yoo , Jeong-wook Kim , Soo-jung Ryu , Jung-keun Park , Jae-don Lee , Young-sam Shin
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： Provided are a multitasking method and apparatus. By continuously maintaining the intrinsic information of each peripheral processing unit of when a process-centered task is stopped, when a reconfigurable array stops executing the process-centered task and executes a different process-centered task, by stopping executing a control-centered task and executing a reconfiguration task, only when the reconfigurable array receives an execution request of the reconfiguration task while the reconfigurable array is performing the control-centered task, or by causing a predetermined number of processing units to execute each of a plurality of reconfiguration tasks that are to be simultaneously executed by the reconfigurable array, wherein the predetermined number of processing units is set in consideration of an expected data processing amount required for the reconfiguration task, the reconfigurable array can more quickly complete execution of multitasking.
摘要翻译：提供了多任务方法和装置。通过持续维护每个外围处理单元在停止进程中心任务时的固有信息，当可重配置阵列停止执行以过程为中心的任务并执行不同的以过程为中心的任务时，通过停止执行以控制为中心的任务和执行重新配置任务，只有当可重构阵列接收到重新配置任务的执行请求，同时可重构阵列正在执行以控制为中心的任务时，或者通过使预定数量的处理单元执行多个重新配置任务中的每一个，由可重配置阵列同时执行，其中考虑到重新配置任务所需的预期数据处理量来设置预定数量的处理单元，可重构阵列可以更快速地完成多任务的执行。

3. 发明授权

US08154547B2 Method and system for early Z test in title-based three-dimensional rendering 有权
标题翻译：基于标题的三维渲染的早期Z检验方法与系统
公开(公告)号：US08154547B2
公开(公告)日：2012-04-10
申请号：US13090924
申请日：2011-04-20
申请人： Kyoung June Min , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
发明人： Kyoung June Min , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.
摘要翻译：提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

4. 发明申请

US20120036579A1 SYSTEM AND METHOD FOR DETECTING ABNORMAL SIP TRAFFIC ON VOIP NETWORK 审中-公开
标题翻译：用于检测VOIP网络异常SIP交通的系统和方法
公开(公告)号：US20120036579A1
公开(公告)日：2012-02-09
申请号：US12964165
申请日：2010-12-09
申请人： Chang-Yong LEE , Hwan-Kuk KIM , Kyoung-Hee KO , Jeong-Wook KIM , Hyun-Cheol JEONG
发明人： Chang-Yong LEE , Hwan-Kuk KIM , Kyoung-Hee KO , Jeong-Wook KIM , Hyun-Cheol JEONG
IPC分类号： G06F12/14
CPC分类号： H04L63/1458 , H04L63/1425
摘要： Provided is a system for detecting abnormal traffic on a network. The system includes: a receiving module which receives session initiation protocol (SIP) traffic information from a network; a decoding module which receives the SIP traffic information from the receiving module and decodes the received SIP traffic information; a traffic information database (DB) which receives the decoded SIP traffic information from the decoding module and stores the received SIP traffic information; an analysis traffic information DB which collects information from the traffic information DB for a predetermined period and stores the collected information as analysis traffic information; a reference traffic information DB which stores reference traffic information; and an attack detection module which compares the analysis traffic information with the reference traffic information and detects whether analysis traffic is attack traffic.
摘要翻译：提供了一种用于检测网络上的异常业务的系统。该系统包括：从网络接收会话发起协议（SIP）业务信息的接收模块; 解码模块，其从所述接收模块接收所述SIP业务信息，并对所接收的SIP业务信息进行解码; 交通信息数据库（DB），其从解码模块接收解码的SIP业务信息，并存储所接收的SIP业务信息; 分析交通信息DB，其从交通信息DB收集预定时间段的信息，并将所收集的信息存储为分析交通信息; 参考交通信息DB，其存储参考交通信息; 以及攻击检测模块，其将分析业务信息与参考业务信息进行比较，并检测分析业务是否是攻击流量。

5. 发明授权

US08019982B2 Loop data processing system and method for dividing a loop into phases 有权
标题翻译：循环数据处理系统和将循环分为阶段的方法
公开(公告)号：US08019982B2
公开(公告)日：2011-09-13
申请号：US11542118
申请日：2006-10-04
申请人： Hong-seok Kim , Suk-jin Kim , Jeong-wook Kim , Soo-jung Ryu
发明人： Hong-seok Kim , Suk-jin Kim , Jeong-wook Kim , Soo-jung Ryu
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/3879
摘要： A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array according to a set of configuration bits; and a centralized register file which allows data used in the program execution to be shared by the processor core and the loop accelerator. The loop accelerator divides the configuration of the array into at least three phases according to whether data exchange with the central register file is conducted during the loop execution. Thus, unnecessary occupation of the routing resource, which is used for the data exchange between the loop accelerator and the central register file during the loop execution, can be avoided.
摘要翻译：一种数据处理系统和方法。数据处理系统包括执行程序的处理器核心; 循环加速器，其具有由多个数据处理单元组成的阵列，并且通过根据一组配置位配置阵列来执行程序中的循环; 以及允许在程序执行中使用的数据由处理器核和循环加速器共享的集中寄存器文件。根据在循环执行期间是否进行与中央寄存器文件的数据交换，循环加速器将阵列的配置分为至少三个阶段。因此，可以避免在循环执行期间用于循环加速器和中央寄存器文件之间的数据交换的路由资源的不必要的占用。

6. 发明授权

US07660970B2 Register allocation method and system for program compiling 有权
标题翻译：注册分配方法和系统进行程序编译
公开(公告)号：US07660970B2
公开(公告)日：2010-02-09
申请号：US11506887
申请日：2006-08-21
申请人： Suk-jin Kim , Jeong-wook Kim , Hong-seok Kim , Soo-jung Ryu
发明人： Suk-jin Kim , Jeong-wook Kim , Hong-seok Kim , Soo-jung Ryu
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30098 , G06F8/441 , G06F8/4452 , G06F9/3552 , G06F9/3836 , G06F9/384
摘要： Disclosed is a data processing system and method. The data processing method determines the number of static registers and the number of rotating registers for assigning a register to a variable contained in a certain program, assigns the register to the variable based on the number of the static registers and the number of the rotating registers, and compiles the program. Further, the method stores in the special register a value corresponding to the number of the rotating registers in the compiling operation, and obtains a physical address from a logical address of the register based on the value. Accordingly, the present invention provides an aspect of efficiently using register files by dynamically controlling the number of rotating registers and the number of static registers for a software pipelined loop, and has an effect capable of reducing the generations of spill/fill codes unnecessary during program execution to a minimum.
摘要翻译：公开了一种数据处理系统和方法。数据处理方法确定静态寄存器的数量和用于将寄存器分配给包含在某个程序中的变量的旋转寄存器的数量，基于静态寄存器的数量和旋转寄存器的数量将寄存器分配给变量，并编译程序。此外，该方法在特殊寄存器中存储与编译操作中的旋转寄存器的数量相对应的值，并且基于该值从寄存器的逻辑地址获得物理地址。因此，本发明提供了通过动态地控制旋转寄存器的数量和用于软件流水线循环的静态寄存器的数量来有效地使用寄存器文件的方面，并且具有能够减少在程序期间不必要的溢出/填充代码的代数的效果执行到最小。

7. 发明申请

US20080018664A1 Method and system for tile binning using half-plane edge function 有权
标题翻译：使用半平面边缘函数的瓦片合并的方法和系统
公开(公告)号：US20080018664A1
公开(公告)日：2008-01-24
申请号：US11604691
申请日：2006-11-28
申请人： Kyoung June Min , Jeong Wook Kim , Dong Soo Kang , Suk Jin Kim , Hee Seok Kim , Seok Yoon Jung , Sang Oak Woo
发明人： Kyoung June Min , Jeong Wook Kim , Dong Soo Kang , Suk Jin Kim , Hee Seok Kim , Seok Yoon Jung , Sang Oak Woo
IPC分类号： G09G5/00
CPC分类号： G06T15/00
摘要： A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.
摘要翻译：一种瓦片合并方法，包括：将用于渲染三角形的场景划分成多个瓦片; 确定每个瓦片的瓦片节点的识别值; 以及基于每个瓦片的瓦片节点的标识值，从瓦片识别包括三角形的整体或部分的瓦片。

8. 发明申请

US20070150710A1 Apparatus and method for optimizing loop buffer in reconfigurable processor 有权
标题翻译：用于优化可重构处理器中循环缓冲器的装置和方法
公开(公告)号：US20070150710A1
公开(公告)日：2007-06-28
申请号：US11525913
申请日：2006-09-25
申请人： Soo Jung Ryu , Jeong Wook Kim , Suk Jin Kim , Hong-Seok Kim
发明人： Soo Jung Ryu , Jeong Wook Kim , Suk Jin Kim , Hong-Seok Kim
IPC分类号： G06F9/44
CPC分类号： G06F17/5054 , G06F9/381 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.
摘要翻译：一种可重配置处理器，包括用于存储用于至少一个环路配置的配置位的配置存储器; 用于存储指示循环中的操作是否为延迟操作的位信息的有效信息存储器; 以及至少一个处理单元，用于通过参考从有效信息存储器发送的比特信息来确定下一个周期中的操作是否是延迟操作，并且根据来自所述有用信息存储器的配置位选择性地执行改变和配置的实现基于确定结果的配置存储器。

9. 发明申请

US20110138462A1 SYSTEM AND METHOD FOR DETECTING VOIP TOLL FRAUD ATTACK FOR INTERNET TELEPHONE 审中-公开
标题翻译：用于检测互联网电话的VOIP TOLL FRAUD攻击的系统和方法
公开(公告)号：US20110138462A1
公开(公告)日：2011-06-09
申请号：US12646174
申请日：2009-12-23
申请人： Jeong-Wook Kim , Hwan-Kuk Kim , Hyun-Cheol Jeong , Yoo-Jae Won , Seok-Ung Yoon , Jong-II Jeong , Kyoung-Hee Ko
发明人： Jeong-Wook Kim , Hwan-Kuk Kim , Hyun-Cheol Jeong , Yoo-Jae Won , Seok-Ung Yoon , Jong-II Jeong , Kyoung-Hee Ko
IPC分类号： G06F11/00
CPC分类号： H04L63/0236 , H04L63/1441 , H04L63/1458 , H04L65/1006 , H04L65/1069 , H04L65/1073
摘要： Provided is a system for detecting a voice over Internet protocol (VoIP) toll fraud attack. The system includes: a database (DB) storing registration information of normal users; a packet reception module receiving a call set-up packet from a network; and a VoIP signaling message forgery/falsification detection module receiving the call set-up packet from the packet reception module and comparing sender address information or header information of the call set-up packet with the registration information stored in the DB to detect whether the call set-up packet is a packet received from one of the normal users.
摘要翻译：提供了一种用于检测因特网协议语音（VoIP）长途欺诈攻击的系统。该系统包括：存储正常用户的登记信息的数据库（DB）; 分组接收模块，从网络接收呼叫建立分组; VoIP信令消息伪造/伪造检测模块从分组接收模块接收呼叫建立分组，并将呼叫建立分组的发送方地址信息或报头信息与DB中存储的登记信息进行比较，以检测呼叫设置分组是从正常用户之一接收的分组。

10. 发明申请

US20080120493A1 Profiler for optimizing processor architecture and application 有权
标题翻译： Profiler用于优化处理器架构和应用
公开(公告)号：US20080120493A1
公开(公告)日：2008-05-22
申请号：US11730170
申请日：2007-03-29
申请人： Dong-Hoon Yoo , Soo Jung Ryu , Jeong-Wook Kim , Hong-Seok Kim , Hee Seok Kim
发明人： Dong-Hoon Yoo , Soo Jung Ryu , Jeong-Wook Kim , Hong-Seok Kim , Hee Seok Kim
IPC分类号： G06F7/38
CPC分类号： G06F8/443 , G06F17/5045 , G06F2217/68
摘要： A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.
摘要翻译：提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

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