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1. 发明申请

US20080120493A1 Profiler for optimizing processor architecture and application 有权
标题翻译： Profiler用于优化处理器架构和应用
公开(公告)号：US20080120493A1
公开(公告)日：2008-05-22
申请号：US11730170
申请日：2007-03-29
申请人： Dong-Hoon Yoo , Soo Jung Ryu , Jeong-Wook Kim , Hong-Seok Kim , Hee Seok Kim
发明人： Dong-Hoon Yoo , Soo Jung Ryu , Jeong-Wook Kim , Hong-Seok Kim , Hee Seok Kim
IPC分类号： G06F7/38
CPC分类号： G06F8/443 , G06F17/5045 , G06F2217/68
摘要： A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.
摘要翻译：提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

2. 发明授权

US08490066B2 Profiler for optimizing processor architecture and application 有权
标题翻译： Profiler用于优化处理器架构和应用
公开(公告)号：US08490066B2
公开(公告)日：2013-07-16
申请号：US11730170
申请日：2007-03-29
申请人： Dong-Hoon Yoo , Soo-Jung Ryu , Jeong-Wook Kim , Hong-Seok Kim , Hee Seok Kim
发明人： Dong-Hoon Yoo , Soo-Jung Ryu , Jeong-Wook Kim , Hong-Seok Kim , Hee Seok Kim
IPC分类号： G06F15/76 , G06F9/44
CPC分类号： G06F8/443 , G06F17/5045 , G06F2217/68
摘要： A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.
摘要翻译：提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

3. 发明授权

US09152418B2 Apparatus and method of exception handling for reconfigurable architecture 有权
标题翻译：可重构架构异常处理的装置和方法
公开(公告)号：US09152418B2
公开(公告)日：2015-10-06
申请号：US11487407
申请日：2006-07-17
申请人： Hee Seok Kim , Dong-Hoon Yoo , Jeong Wook Kim , Soo Jung Ryu
发明人： Hee Seok Kim , Dong-Hoon Yoo , Jeong Wook Kim , Soo Jung Ryu
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/30105 , G06F9/30116 , G06F9/30123 , G06F9/3863
摘要： A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.
摘要翻译：一种处理器，包括包括多个处理元件的粗粒子阵列，包括第一多个寄存器文件的中央寄存器文件，包括第二多个寄存器文件的影子中心寄存器文件，与每个寄存器文件相对应的第二多个寄存器堆中的每一个包括在中央寄存器文件中的第一多个寄存器文件和多个影子寄存器文件，多个影子寄存器文件中的每一个对应于包括在从多个寄存器文件中选择的预定处理元件中的第三多个寄存器文件中的每一个处理元件。

4. 发明授权

US07529917B2 Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array 有权
标题翻译：在可重构粗粒度阵列中循环处理中的中断处理方法和装置
公开(公告)号：US07529917B2
公开(公告)日：2009-05-05
申请号：US11519858
申请日：2006-09-13
申请人： Soo Jung Ryu , Jeong Wook Kim , Dong-Hoon Yoo , Hee Seok Kim
发明人： Soo Jung Ryu , Jeong Wook Kim , Dong-Hoon Yoo , Hee Seok Kim
IPC分类号： G06F9/00
CPC分类号： G06F9/4812
摘要： A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.
摘要翻译：一种包括包括多个功能单元和多个寄存器文件的粗粒度阵列的处理器，其中由粗粒度阵列执行的循环被分割成多个子循环，并且当执行中断请求时发生中断请求在粗粒子数组中的子循环，中断请求在子循环执行完成后被处理。

5. 发明授权

US08024717B2 Method and apparatus for efficiently processing array operation in computer system 有权
标题翻译：在计算机系统中有效处理阵列运算的方法和装置
公开(公告)号：US08024717B2
公开(公告)日：2011-09-20
申请号：US11492974
申请日：2006-07-26
申请人： Dong-Hoon Yoo , Hee Seok Kim , Jeong Wook Kim , Soo Jung Ryu
发明人： Dong-Hoon Yoo , Hee Seok Kim , Jeong Wook Kim , Soo Jung Ryu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452
摘要： An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional arrays; and transforming each of the plurality of unrolled multi-dimensional arrays into a one-dimensional array having an array subscript expression in a form of an affine function with respect to a loop counter variable.
摘要翻译：一种用于处理计算机系统中的循环中的阵列的装置和方法，包括：基于预定的展开因子将循环展开应用到包括在循环中的多维阵列，以生成多个展开的多维阵列; 并且将多个展开的多维数组中的每一个变换成具有相对于循环计数器变量的仿射函数形式的数组下标表达式的一维阵列。

6. 发明授权

US07836291B2 Method, medium, and apparatus with interrupt handling in a reconfigurable array 有权
标题翻译：在可重构阵列中具有中断处理的方法，介质和设备
公开(公告)号：US07836291B2
公开(公告)日：2010-11-16
申请号：US11581366
申请日：2006-10-17
申请人： Keun Soo Yim , Jeong Wook Kim , Soo Jung Ryu , Jung Keun Park , Jeong Joon Yoo , Dong-Hoon Yoo , Chae Seok Im , Jae Don Lee , Hee Seok Kim
发明人： Keun Soo Yim , Jeong Wook Kim , Soo Jung Ryu , Jung Keun Park , Jeong Joon Yoo , Dong-Hoon Yoo , Chae Seok Im , Jae Don Lee , Hee Seok Kim
IPC分类号： G06F9/00 , G06F13/24
CPC分类号： H03K19/177 , G06F9/4812
摘要： A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.
摘要翻译：一种用于有效处理可重构阵列中的中断的方法，介质和装置。在该方法中，当发生中断请求时，可重配置阵列暂停执行操作，并且在存储要用于处理中断请求的寄存器的寄存器值之后，响应于可重构阵列的选择处理单元执行中断服务到中断请求。完成中断服务后，寄存器值被恢复，并且可重新配置的阵列恢复执行该操作。

7. 发明申请

US20070186085A1 Method, medium, and apparatus with interrupt handling in a reconfigurable array 有权
标题翻译：在可重构阵列中具有中断处理的方法，介质和设备
公开(公告)号：US20070186085A1
公开(公告)日：2007-08-09
申请号：US11581366
申请日：2006-10-17
申请人： Keun Soo Yim , Jeong Wook Kim , Soo Jung Ryu , Jung Keun Park , Jeong Joon Yoo , Dong-Hoon Yoo , Chae Seok Im , Jae Don Lee , Hee Seok Kim
发明人： Keun Soo Yim , Jeong Wook Kim , Soo Jung Ryu , Jung Keun Park , Jeong Joon Yoo , Dong-Hoon Yoo , Chae Seok Im , Jae Don Lee , Hee Seok Kim
IPC分类号： G06F7/38
CPC分类号： H03K19/177 , G06F9/4812
摘要： A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.
摘要翻译：一种用于有效处理可重构阵列中的中断的方法，介质和装置。在该方法中，当发生中断请求时，可重配置阵列暂停执行操作，并且在存储要用于处理中断请求的寄存器的寄存器值之后，响应于可重构阵列的选择处理单元执行中断服务到中断请求。完成中断服务后，寄存器值被恢复，并且可重新配置的阵列恢复执行该操作。

8. 发明申请

US20070169044A1 Method and apparatus for efficiently processing array operation in computer system 有权
标题翻译：在计算机系统中有效处理阵列运算的方法和装置
公开(公告)号：US20070169044A1
公开(公告)日：2007-07-19
申请号：US11492974
申请日：2006-07-26
申请人： Dong-Hoon Yoo , Hee Seok Kim , Jeong Wook Kim , Soo Jung Ryu
发明人： Dong-Hoon Yoo , Hee Seok Kim , Jeong Wook Kim , Soo Jung Ryu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452
摘要： An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional arrays; and transforming each of the plurality of unrolled multi-dimensional arrays into a one-dimensional array having an array subscript expression in a form of an affine function with respect to a loop counter variable.
摘要翻译：一种用于处理计算机系统中的循环中的阵列的装置和方法，包括：基于预定的展开因子将循环展开应用到包括在循环中的多维阵列，以生成多个展开的多维阵列; 并且将多个展开的多维数组中的每一个变换成具有相对于循环计数器变量的仿射函数形式的数组下标表达式的一维阵列。

9. 发明申请

US20070162729A1 Method and apparatus for interrupt handling in coarse grained array 有权
标题翻译：粗粒度阵列中断处理的方法和装置
公开(公告)号：US20070162729A1
公开(公告)日：2007-07-12
申请号：US11519858
申请日：2006-09-13
申请人： Soo Jung Ryu , Jeong Wook Kim , Dong-Hoon Yoo , Hee Seok Kim
发明人： Soo Jung Ryu , Jeong Wook Kim , Dong-Hoon Yoo , Hee Seok Kim
IPC分类号： G06F9/44
CPC分类号： G06F9/4812
摘要： A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.
摘要翻译：一种包括包括多个功能单元和多个寄存器文件的粗粒度阵列的处理器，其中由粗粒度阵列执行的循环被分割成多个子循环，并且当执行中断请求时发生中断请求在粗粒子数组中的子循环，中断请求在子循环执行完成后被处理。

10. 发明授权

US07779225B2 Memory access method using three dimensional address mapping 有权
标题翻译：内存访问方法使用三维地址映射
公开(公告)号：US07779225B2
公开(公告)日：2010-08-17
申请号：US11828440
申请日：2007-07-26
申请人： Jong Myon Kim , Soojung Ryu , Dong-Hoon Yoo , Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Kyoung June Min
发明人： Jong Myon Kim , Soojung Ryu , Dong-Hoon Yoo , Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Kyoung June Min
IPC分类号： G06F12/00
CPC分类号： G06F8/443 , G06F8/447 , G06F12/0207
摘要： A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.
摘要翻译：存储器访问方法包括：从程序中用于访问具有三重循环的存储器的程序代码获取a，b和c，所述三循环的最内循环变量可以具有多个值，b 是三重循环的中间循环变量可能具有的多个值，c是三重循环的最外圈循环变量可能具有的值的数量; 获取由三重循环访问的存储器的起始地址; 并使用起始地址和功能获得由三重回路访问的存储器的a×b×c个地址。

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