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1. 发明授权

US07590831B2 Loop accelerator and data processing system having the same 有权
标题翻译：循环加速器和数据处理系统具有相同的功能
公开(公告)号：US07590831B2
公开(公告)日：2009-09-15
申请号：US11514889
申请日：2006-09-05
申请人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-Seok Kim , Jun-jin Kong
发明人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-Seok Kim , Jun-jin Kong
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3877 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.
摘要翻译：提供了一种环路加速器和具有环路加速器的数据处理系统。数据处理系统包括执行程序的循环部分的循环加速器，处理除循环部分之外的程序的剩余部分的处理器核心以及在处理器核心和循环加速器之间传送数据的中央寄存器文件。环路加速器包括多个处理元件（PE），每个处理元件（PE）对每个字执行操作以执行程序;配置存储器，其存储指示PE的操作，状态等的配置位，以及多个上下文存储器安装在PE的列或行方向上，其沿着PE排列的方向传送配置位。因此，可以简化配置存储器和PE之间的连接结构，以容易地修改循环加速器的结构，以便扩展循环加速器。

2. 发明申请

US20070094485A1 Data processing system and method 有权
标题翻译：数据处理系统及方法
公开(公告)号：US20070094485A1
公开(公告)日：2007-04-26
申请号：US11542118
申请日：2006-10-04
申请人： Hong-seok Kim , Suk-jin Kim , Jeong-wook Kim , Soo-jung Ryu
发明人： Hong-seok Kim , Suk-jin Kim , Jeong-wook Kim , Soo-jung Ryu
IPC分类号： G06F9/44
CPC分类号： G06F9/325 , G06F9/3879
摘要： A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array according to a set of configuration bits; and a centralized register file which allows data used in the program execution to be shared by the processor core and the loop accelerator. The loop accelerator divides the configuration of the array into at least three phases according to whether data exchange with the central register file is conducted during the loop execution. Thus, unnecessary occupation of the routing resource, which is used for the data exchange between the loop accelerator and the central register file during the loop execution, can be avoided.
摘要翻译：一种数据处理系统和方法。数据处理系统包括执行程序的处理器核心; 循环加速器，其具有由多个数据处理单元组成的阵列，并且通过根据一组配置位配置阵列来执行程序中的循环; 以及允许在程序执行中使用的数据由处理器核和循环加速器共享的集中寄存器文件。根据在循环执行期间是否进行与中央寄存器文件的数据交换，循环加速器将阵列的配置分为至少三个阶段。因此，可以避免在循环执行期间用于循环加速器和中央寄存器文件之间的数据交换的路由资源的不必要的占用。

3. 发明授权

US08019982B2 Loop data processing system and method for dividing a loop into phases 有权
标题翻译：循环数据处理系统和将循环分为阶段的方法
公开(公告)号：US08019982B2
公开(公告)日：2011-09-13
申请号：US11542118
申请日：2006-10-04
申请人： Hong-seok Kim , Suk-jin Kim , Jeong-wook Kim , Soo-jung Ryu
发明人： Hong-seok Kim , Suk-jin Kim , Jeong-wook Kim , Soo-jung Ryu
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/3879
摘要： A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array according to a set of configuration bits; and a centralized register file which allows data used in the program execution to be shared by the processor core and the loop accelerator. The loop accelerator divides the configuration of the array into at least three phases according to whether data exchange with the central register file is conducted during the loop execution. Thus, unnecessary occupation of the routing resource, which is used for the data exchange between the loop accelerator and the central register file during the loop execution, can be avoided.
摘要翻译：一种数据处理系统和方法。数据处理系统包括执行程序的处理器核心; 循环加速器，其具有由多个数据处理单元组成的阵列，并且通过根据一组配置位配置阵列来执行程序中的循环; 以及允许在程序执行中使用的数据由处理器核和循环加速器共享的集中寄存器文件。根据在循环执行期间是否进行与中央寄存器文件的数据交换，循环加速器将阵列的配置分为至少三个阶段。因此，可以避免在循环执行期间用于循环加速器和中央寄存器文件之间的数据交换的路由资源的不必要的占用。

4. 发明授权

US07660970B2 Register allocation method and system for program compiling 有权
标题翻译：注册分配方法和系统进行程序编译
公开(公告)号：US07660970B2
公开(公告)日：2010-02-09
申请号：US11506887
申请日：2006-08-21
申请人： Suk-jin Kim , Jeong-wook Kim , Hong-seok Kim , Soo-jung Ryu
发明人： Suk-jin Kim , Jeong-wook Kim , Hong-seok Kim , Soo-jung Ryu
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30098 , G06F8/441 , G06F8/4452 , G06F9/3552 , G06F9/3836 , G06F9/384
摘要： Disclosed is a data processing system and method. The data processing method determines the number of static registers and the number of rotating registers for assigning a register to a variable contained in a certain program, assigns the register to the variable based on the number of the static registers and the number of the rotating registers, and compiles the program. Further, the method stores in the special register a value corresponding to the number of the rotating registers in the compiling operation, and obtains a physical address from a logical address of the register based on the value. Accordingly, the present invention provides an aspect of efficiently using register files by dynamically controlling the number of rotating registers and the number of static registers for a software pipelined loop, and has an effect capable of reducing the generations of spill/fill codes unnecessary during program execution to a minimum.
摘要翻译：公开了一种数据处理系统和方法。数据处理方法确定静态寄存器的数量和用于将寄存器分配给包含在某个程序中的变量的旋转寄存器的数量，基于静态寄存器的数量和旋转寄存器的数量将寄存器分配给变量，并编译程序。此外，该方法在特殊寄存器中存储与编译操作中的旋转寄存器的数量相对应的值，并且基于该值从寄存器的逻辑地址获得物理地址。因此，本发明提供了通过动态地控制旋转寄存器的数量和用于软件流水线循环的静态寄存器的数量来有效地使用寄存器文件的方面，并且具有能够减少在程序期间不必要的溢出/填充代码的代数的效果执行到最小。

5. 发明申请

US20070169032A1 Data processing system and method 有权
标题翻译：数据处理系统及方法
公开(公告)号：US20070169032A1
公开(公告)日：2007-07-19
申请号：US11506887
申请日：2006-08-21
申请人： Suk-jin Kim , Jeong-wook Kim , Hong-seok Kim , Soo-jung Ryu
发明人： Suk-jin Kim , Jeong-wook Kim , Hong-seok Kim , Soo-jung Ryu
IPC分类号： G06F9/45
CPC分类号： G06F9/30098 , G06F8/441 , G06F8/4452 , G06F9/3552 , G06F9/3836 , G06F9/384
摘要： Disclosed is a data processing system and method. The data processing method determines the number of static registers and the number of rotating registers for assigning a register to a variable contained in a certain program, assigns the register to the variable based on the number of the static registers and the number of the rotating registers, and compiles the program. Further, the method stores in the special register a value corresponding to the number of the rotating registers in the compiling operation, and obtains a physical address from a logical address of the register based on the value. Accordingly, the present invention provides an aspect of efficiently using register files by dynamically controlling the number of rotating registers and the number of static registers for a software pipelined loop, and has an effect capable of reducing the generations of spill/fill codes unnecessary during program execution to a minimum.
摘要翻译：公开了一种数据处理系统和方法。数据处理方法确定静态寄存器的数量和用于将寄存器分配给包含在某个程序中的变量的旋转寄存器的数量，基于静态寄存器的数量和旋转寄存器的数量将寄存器分配给变量，并编译程序。此外，该方法在特殊寄存器中存储与编译操作中的旋转寄存器的数量相对应的值，并且基于该值从寄存器的逻辑地址获得物理地址。因此，本发明提供了通过动态地控制旋转寄存器的数量和用于软件流水线循环的静态寄存器的数量来有效地使用寄存器文件的方面，并且具有能够减少在程序期间不必要的溢出/填充代码的代数的效果执行到最小。

6. 发明申请

US20070157009A1 Loop accelerator and data processing system having the same 有权
标题翻译：循环加速器和数据处理系统具有相同的功能
公开(公告)号：US20070157009A1
公开(公告)日：2007-07-05
申请号：US11514889
申请日：2006-09-05
申请人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-seok Kim , Jun-jin Kong
发明人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-seok Kim , Jun-jin Kong
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3877 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.
摘要翻译：提供了一种环路加速器和具有环路加速器的数据处理系统。数据处理系统包括执行程序的循环部分的循环加速器，处理除循环部分之外的程序的剩余部分的处理器核心以及在处理器核心和循环加速器之间传送数据的中央寄存器文件。环路加速器包括多个处理元件（PE），每个处理元件（PE）对每个字执行操作以执行程序;配置存储器，其存储指示PE的操作，状态等的配置位，以及多个上下文存储器安装在PE的列或行方向上，其沿着PE排列的方向传送配置位。因此，可以简化配置存储器和PE之间的连接结构，以容易地修改循环加速器的结构，以便扩展循环加速器。

7. 发明授权

US08645955B2 Multitasking method and apparatus for reconfigurable array 有权
标题翻译：用于可重构阵列的多任务方法和装置
公开(公告)号：US08645955B2
公开(公告)日：2014-02-04
申请号：US11808750
申请日：2007-06-12
申请人： Keun-soo Yim , Jeong-joon Yoo , Jeong-wook Kim , Soo-jung Ryu , Jung-keun Park , Jae-don Lee , Young-sam Shin
发明人： Keun-soo Yim , Jeong-joon Yoo , Jeong-wook Kim , Soo-jung Ryu , Jung-keun Park , Jae-don Lee , Young-sam Shin
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： Provided are a multitasking method and apparatus. By continuously maintaining the intrinsic information of each peripheral processing unit of when a process-centered task is stopped, when a reconfigurable array stops executing the process-centered task and executes a different process-centered task, by stopping executing a control-centered task and executing a reconfiguration task, only when the reconfigurable array receives an execution request of the reconfiguration task while the reconfigurable array is performing the control-centered task, or by causing a predetermined number of processing units to execute each of a plurality of reconfiguration tasks that are to be simultaneously executed by the reconfigurable array, wherein the predetermined number of processing units is set in consideration of an expected data processing amount required for the reconfiguration task, the reconfigurable array can more quickly complete execution of multitasking.
摘要翻译：提供了多任务方法和装置。通过持续维护每个外围处理单元在停止进程中心任务时的固有信息，当可重配置阵列停止执行以过程为中心的任务并执行不同的以过程为中心的任务时，通过停止执行以控制为中心的任务和执行重新配置任务，只有当可重构阵列接收到重新配置任务的执行请求，同时可重构阵列正在执行以控制为中心的任务时，或者通过使预定数量的处理单元执行多个重新配置任务中的每一个，由可重配置阵列同时执行，其中考虑到重新配置任务所需的预期数据处理量来设置预定数量的处理单元，可重构阵列可以更快速地完成多任务的执行。

8. 发明申请

US20070288930A1 Multitasking method and apparatus for reconfigurable array 有权
标题翻译：用于可重构阵列的多任务方法和装置
公开(公告)号：US20070288930A1
公开(公告)日：2007-12-13
申请号：US11808750
申请日：2007-06-12
申请人： Keun-soo Yim , Jeong-joon Yoo , Jeong-wook Kim , Soo-jung Ryu , Jung-keun Park , Jae-don Lee , Young-sam Shin
发明人： Keun-soo Yim , Jeong-joon Yoo , Jeong-wook Kim , Soo-jung Ryu , Jung-keun Park , Jae-don Lee , Young-sam Shin
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： Provided are a multitasking method and apparatus. By continuously maintaining the intrinsic information of each peripheral processing unit of when a process-centered task is stopped, when a reconfigurable array stops executing the process-centered task and executes a different process-centered task, by stopping executing a control-centered task and executing a reconfiguration task, only when the reconfigurable array receives an execution request of the reconfiguration task while the reconfigurable array is performing the control-centered task, or by causing a predetermined number of processing units to execute each of a plurality of reconfiguration tasks that are to be simultaneously executed by the reconfigurable array, wherein the predetermined number of processing units is set in consideration of an expected data processing amount required for the reconfiguration task, the reconfigurable array can more quickly complete execution of multitasking.
摘要翻译：提供了多任务方法和装置。通过持续维护每个外围处理单元在停止进程中心任务时的固有信息，当可重配置阵列停止执行以过程为中心的任务并执行不同的以过程为中心的任务时，通过停止执行以控制为中心的任务和执行重新配置任务，只有当可重构阵列接收到重新配置任务的执行请求，同时可重构阵列正在执行以控制为中心的任务时，或者通过使预定数量的处理单元执行多个重新配置任务中的每一个，由可重配置阵列同时执行，其中考虑到重新配置任务所需的预期数据处理量来设置预定数量的处理单元，可重构阵列可以更快速地完成多任务的执行。

9. 发明授权

US08417918B2 Reconfigurable processor with designated processing elements and reserved portion of register file for interrupt processing 有权
标题翻译：具有指定处理元件的可重构处理器和用于中断处理的寄存器文件的保留部分
公开(公告)号：US08417918B2
公开(公告)日：2013-04-09
申请号：US12709862
申请日：2010-02-22
申请人： Bernhard Egger , Dong-hoon Yoo , Soo-jung Ryu , Il-hyun Park
发明人： Bernhard Egger , Dong-hoon Yoo , Soo-jung Ryu , Il-hyun Park
IPC分类号： G06F15/16
CPC分类号： G06F13/24
摘要： An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel.
摘要翻译：提供中断处理技术和可重构处理器。可重构处理器包括多个处理元件，并且一些处理元件被指定用于中断处理。当可重构处理器执行循环操作时发生中断请求时，指定的处理单元可以处理中断请求。中断处理技术允许并行处理中断请求和循环操作。

10. 发明授权

US08516231B2 Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus 有权
标题翻译：包含中断处理装置的等模型处理器和处理器的中断处理装置和方法
公开(公告)号：US08516231B2
公开(公告)日：2013-08-20
申请号：US12695266
申请日：2010-01-28
申请人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger
发明人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3836 , G06F9/327
摘要： An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.
摘要翻译：提供了一种用于等模型处理器的中断支持确定装置和方法，以及包括中断支持确定装置的处理器。中断支持确定装置确定输入到处理器解码器的指令是否是多等待时间指令，如果指令是多等待时间指令，则将指令的当前等待时间与剩余延迟进行比较，并将当前等待时间更新为剩余延迟，如果当前的延迟大于剩余的延迟。

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