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1. 发明申请

US20110210662A1 PLASMA DISPLAY APPARATUS 失效
标题翻译：等离子显示设备
公开(公告)号：US20110210662A1
公开(公告)日：2011-09-01
申请号：US12667962
申请日：2009-02-12
申请人： Kyeong Cheol Seo , Duk Gyu Jang , Jeong Sik Choi , Tae Hwa Hwang
发明人： Kyeong Cheol Seo , Duk Gyu Jang , Jeong Sik Choi , Tae Hwa Hwang
IPC分类号： H01J17/49
CPC分类号： H01J11/32 , H01J11/12 , H01J11/24 , H01J11/44 , H01J2211/245 , H01J2211/323 , H01J2211/444
摘要： The present invention relates to a plasma display apparatus. The plasma display apparatus comprises an upper substrate, a first electrode and a second electrode formed on the upper substrate, a lower substrate disposed to face the upper substrate, and a third electrode and a barrier rib formed in the lower substrate. First and second black matrices are formed in the upper substrate and are separated from each other on a same straight line. According to the present invention, while maintaining the function of improving a contrast ratio and reflectance of a black matrix, a short and a spotted pattern that may occur when simultaneous exposure is performed can be reduced, and so the picture quality, the cost of production, and efficiency can be improved.
摘要翻译：等离子体显示装置技术领域本发明涉及等离子体显示装置。等离子体显示装置包括上基板，第一电极和形成在上基板上的第二电极，设置成面对上基板的下基板，以及形成在下基板中的第三电极和阻挡肋。第一和第二黑色矩阵形成在上基板中并且在相同的直线上彼此分离。根据本发明，在保持提高对比度和黑矩阵的反射率的功能的同时，可以减少在同时曝光时可能发生的短路和点状图案，因此图像质量，生产成本，效率可以提高。

2. 发明授权

US07304367B2 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs 有权
标题翻译：金属绝缘体金属电容器，包括掺杂多晶硅接触插头上的过渡金属硅化物膜
公开(公告)号：US07304367B2
公开(公告)日：2007-12-04
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

3. 发明授权

US06995071B2 Methods of forming MIM type capacitor structures using low temperature plasma processing 有权
标题翻译：使用低温等离子体处理形成MIM型电容器结构的方法
公开(公告)号：US06995071B2
公开(公告)日：2006-02-07
申请号：US10830214
申请日：2004-04-22
申请人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
发明人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
IPC分类号： H10L21/8242
CPC分类号： H01L27/10852 , C23C16/405 , C23C16/56 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/02356 , H01L21/31645 , H01L27/10817 , H01L27/10855 , H01L28/91 , Y10S438/957
摘要： Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.
摘要翻译：在集成电路存储器件中形成金属 - 绝缘体 - 金属型电容器的方法可以包括在低温等离子体处理中在电容器结构的下部电极上结晶HfO 2/2电介质层，温度范围为约250摄氏度和约450摄氏度。上电极可以形成在HfO 2 2电介质层上。

4. 发明授权

US07569992B2 Plasma display panel and manufacturing method thereof 失效
标题翻译：等离子显示面板及其制造方法
公开(公告)号：US07569992B2
公开(公告)日：2009-08-04
申请号：US11324341
申请日：2006-01-04
申请人： Jeong Sik Choi , Eung Chul Park
发明人： Jeong Sik Choi , Eung Chul Park
IPC分类号： H01J17/49
CPC分类号： H01J11/12 , H01J11/40
摘要： Disclosed are a plasma display panel and a method of manufacturing the same. The plasma display panel according to the present invention comprises a front panel comprising a protective layer and a rear panel disposed apart from the front panel by a predetermined distance. The protective layer comprising magnesium oxide (MgO) is doped with scandium (Sc) and calcium (Ca). The plasma display panel according to the present invention has the advantage of excellent temperature-dependent panel characteristic. The plasma display panel according to the present invention also has the further advantage of excellent voltage margin of the address voltage.
摘要翻译：公开了等离子体显示面板及其制造方法。根据本发明的等离子体显示面板包括前面板，其包括保护层和与前面板隔开预定距离设置的后面板。包含氧化镁（MgO）的保护层掺杂有钪（Sc）和钙（Ca）。根据本发明的等离子体显示面板具有优异的温度依赖性面板特性。根据本发明的等离子体显示面板还具有地址电压优异的电压裕度的另外的优点。

5. 发明授权

US08232726B2 Plasma display apparatus with black matrices 失效
标题翻译：带黑色矩阵的等离子显示装置
公开(公告)号：US08232726B2
公开(公告)日：2012-07-31
申请号：US12667962
申请日：2009-02-12
申请人： Kyeong Cheol Seo , Duk Gyu Jang , Jeong Sik Choi , Tae Hwa Hwang
发明人： Kyeong Cheol Seo , Duk Gyu Jang , Jeong Sik Choi , Tae Hwa Hwang
IPC分类号： H01J17/49
CPC分类号： H01J11/32 , H01J11/12 , H01J11/24 , H01J11/44 , H01J2211/245 , H01J2211/323 , H01J2211/444
摘要： The present invention relates to a plasma display apparatus. The plasma display apparatus comprises an upper substrate, a first electrode and a second electrode formed on the upper substrate, a lower substrate disposed to face the upper substrate, and a third electrode and a barrier rib formed in the lower substrate. First and second black matrices are formed in the upper substrate and are separated from each other on a same straight line. According to the present invention, while maintaining the function of improving a contrast ratio and reflectance of a black matrix, a short and a spotted pattern that may occur when simultaneous exposure is performed can be reduced, and so the picture quality, the cost of production, and efficiency can be improved.
摘要翻译：等离子体显示装置技术领域本发明涉及等离子体显示装置。等离子体显示装置包括上基板，第一电极和形成在上基板上的第二电极，设置成面对上基板的下基板，以及形成在下基板中的第三电极和阻挡肋。第一和第二黑色矩阵形成在上基板中并且在相同的直线上彼此分离。根据本发明，在保持提高对比度和黑矩阵的反射率的功能的同时，可以减少在同时曝光时可能发生的短路和点状图案，因此图像质量，生产成本，效率可以提高。

6. 发明授权

US07314806B2 Methods of forming metal-insulator-metal (MIM) capacitors with separate seed 有权
标题翻译：用分离的种子形成金属 - 绝缘体 - 金属（MIM）电容器的方法
公开(公告)号：US07314806B2
公开(公告)日：2008-01-01
申请号：US11097404
申请日：2005-04-01
申请人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
发明人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
IPC分类号： H01L21/20
CPC分类号： H01L21/31122
摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
摘要翻译：可以在金属 - 绝缘体 - 金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮化物种子电介质层。金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应电容器。包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

7. 发明授权

US07495292B2 Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate 失效
标题翻译：在电池阵列中具有垫接触插塞的集成电路器件和集成电路衬底的外围电路区域
公开(公告)号：US07495292B2
公开(公告)日：2009-02-24
申请号：US11713160
申请日：2007-03-02
申请人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
发明人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
IPC分类号： H01L29/76
CPC分类号： H01L27/10855 , H01L21/76889 , H01L21/76895 , H01L27/10817 , H01L27/10894 , H01L27/10897
摘要： Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，例如动态随机存取存储器（DRAM）器件，其包括具有单元阵列区域和外围电路区域的集成电路衬底。在单元阵列区域中的集成电路基板上设置埋入式接触插塞，并且在外围电路区域中的集成电路基板上设置电阻器。第一焊盘接触插头设置在电池阵列区域中的埋入式接触插塞上，并且在外围电路区域中的电阻器上设置第二焊盘接触插头。在第一焊盘接触插塞和埋地接触插头之间以及第二焊盘接触插头和电阻器之间提供欧姆层。还提供了制造集成电路器件的相关方法。

8. 发明授权

US07205219B2 Methods of forming integrated circuits devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate 失效
标题翻译：在集成电路基板的单元阵列和外围电路区域中形成具有焊盘接触插塞的集成电路器件的方法
公开(公告)号：US07205219B2
公开(公告)日：2007-04-17
申请号：US10823221
申请日：2004-04-13
申请人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
发明人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
IPC分类号： H01L21/44
CPC分类号： H01L27/10855 , H01L21/76889 , H01L21/76895 , H01L27/10817 , H01L27/10894 , H01L27/10897
摘要： Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，例如动态随机存取存储器（DRAM）器件，其包括具有单元阵列区域和外围电路区域的集成电路衬底。在单元阵列区域中的集成电路基板上设置埋入式接触插塞，并且在外围电路区域中的集成电路基板上设置电阻器。第一焊盘接触插头设置在电池阵列区域中的埋入式接触插塞上，并且在外围电路区域中的电阻器上设置第二焊盘接触插头。在第一焊盘接触插塞和埋地接触插头之间以及第二焊盘接触插头和电阻器之间提供欧姆层。还提供了制造集成电路器件的相关方法。

9. 发明申请

US20050227432A1 Methods of forming metal-insulator-metal (MIM) capacitors with separate seed and main dielectric layers and MIM capacitors so formed 有权
标题翻译：形成金属 - 绝缘体 - 金属（MIM）电容器的方法，该电容器具有单独的种子和主电介质层以及如此形成的MIM电容器
公开(公告)号：US20050227432A1
公开(公告)日：2005-10-13
申请号：US11097404
申请日：2005-04-01
申请人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
发明人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
IPC分类号： H01L27/108 , H01L21/311 , H01L21/8242
CPC分类号： H01L21/31122
摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
摘要翻译：可以在间绝缘子金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮氧化物种子电介质层。金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应电容器。包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

10. 发明申请

US20050023640A1 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs and methods of forming the same 有权
标题翻译：包括掺杂多晶硅接触插塞上的过渡金属硅化物膜的金属 - 绝缘体 - 金属电容器及其形成方法
公开(公告)号：US20050023640A1
公开(公告)日：2005-02-03
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L27/108 , H01L21/02 , G02F1/136 , H01L21/20 , H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

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