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1. 发明申请

US20070145485A1 Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate 失效
标题翻译：在电池阵列中具有垫接触插塞的集成电路器件和集成电路衬底的外围电路区域
公开(公告)号：US20070145485A1
公开(公告)日：2007-06-28
申请号：US11713160
申请日：2007-03-02
申请人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
发明人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
IPC分类号： H01L23/62
CPC分类号： H01L27/10855 , H01L21/76889 , H01L21/76895 , H01L27/10817 , H01L27/10894 , H01L27/10897
摘要： Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，例如动态随机存取存储器（DRAM）器件，其包括具有单元阵列区域和外围电路区域的集成电路衬底。在单元阵列区域中的集成电路基板上设置埋入式接触插塞，并且在外围电路区域中的集成电路基板上设置电阻器。第一焊盘接触插头设置在电池阵列区域中的埋入式接触插塞上，并且在外围电路区域中的电阻器上设置第二焊盘接触插头。在第一焊盘接触插塞和埋地接触插头之间以及第二焊盘接触插头和电阻器之间提供欧姆层。还提供了制造集成电路器件的相关方法。

2. 发明授权

US07495292B2 Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate 失效
标题翻译：在电池阵列中具有垫接触插塞的集成电路器件和集成电路衬底的外围电路区域
公开(公告)号：US07495292B2
公开(公告)日：2009-02-24
申请号：US11713160
申请日：2007-03-02
申请人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
发明人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
IPC分类号： H01L29/76
CPC分类号： H01L27/10855 , H01L21/76889 , H01L21/76895 , H01L27/10817 , H01L27/10894 , H01L27/10897
摘要： Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，例如动态随机存取存储器（DRAM）器件，其包括具有单元阵列区域和外围电路区域的集成电路衬底。在单元阵列区域中的集成电路基板上设置埋入式接触插塞，并且在外围电路区域中的集成电路基板上设置电阻器。第一焊盘接触插头设置在电池阵列区域中的埋入式接触插塞上，并且在外围电路区域中的电阻器上设置第二焊盘接触插头。在第一焊盘接触插塞和埋地接触插头之间以及第二焊盘接触插头和电阻器之间提供欧姆层。还提供了制造集成电路器件的相关方法。

3. 发明授权

US07205219B2 Methods of forming integrated circuits devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate 失效
标题翻译：在集成电路基板的单元阵列和外围电路区域中形成具有焊盘接触插塞的集成电路器件的方法
公开(公告)号：US07205219B2
公开(公告)日：2007-04-17
申请号：US10823221
申请日：2004-04-13
申请人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
发明人： Se-Hoon Oh , Jung-Hee Chung , Jae-Hyoung Choi , Jeong-Sik Choi , Sung-Tae Kim , Cha-Young Yoo
IPC分类号： H01L21/44
CPC分类号： H01L27/10855 , H01L21/76889 , H01L21/76895 , H01L27/10817 , H01L27/10894 , H01L27/10897
摘要： Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，例如动态随机存取存储器（DRAM）器件，其包括具有单元阵列区域和外围电路区域的集成电路衬底。在单元阵列区域中的集成电路基板上设置埋入式接触插塞，并且在外围电路区域中的集成电路基板上设置电阻器。第一焊盘接触插头设置在电池阵列区域中的埋入式接触插塞上，并且在外围电路区域中的电阻器上设置第二焊盘接触插头。在第一焊盘接触插塞和埋地接触插头之间以及第二焊盘接触插头和电阻器之间提供欧姆层。还提供了制造集成电路器件的相关方法。

4. 发明授权

US07179739B2 Methods of forming a semiconductor device including a metal silicide layer between a conductive plug and a bottom electrode of a capacitor 有权
标题翻译：在电容器的导电插塞和底部电极之间形成包括金属硅化物层的半导体器件的方法
公开(公告)号：US07179739B2
公开(公告)日：2007-02-20
申请号：US10863828
申请日：2004-06-08
申请人： Jeong-Sik Choi , Jung-Hee Chung , Woo-Gwan Shim , Young-Sun Kim , Jae-Hyoung Choi , Se-Hoon Oh , Cha-Young Yoo
发明人： Jeong-Sik Choi , Jung-Hee Chung , Woo-Gwan Shim , Young-Sun Kim , Jae-Hyoung Choi , Se-Hoon Oh , Cha-Young Yoo
IPC分类号： H01L21/44
CPC分类号： H01L28/91 , H01L21/76877 , H01L27/10855 , H01L27/11507 , H01L28/75
摘要： Embodiments of the present invention include methods of forming a contact to a capacitor in a semiconductor device. A metal silicide layer is formed at a top surface of a conductive plug of the semiconductor device that is coupled to a bottom electrode of the capacitor to provide an ohmic contact therebetween. Forming a metal silicide layer may include exposing a surface of the conductive plug, depositing a metal layer of the bottom electrode on the exposed surface of the conductive plug and thermally processing the semiconductor device to react a part of the deposited metal layer and the conductive plug to form the metal silicide layer. Methods of forming a semiconductor device including a capacitor having a metal silicide layer connecting a bottom electrode of the capacitor and a conductive plug are also provided.
摘要翻译：本发明的实施例包括在半导体器件中形成与电容器的接触的方法。金属硅化物层形成在半导体器件的导电插塞的顶表面上，该顶表面耦合到电容器的底部电极以在其间提供欧姆接触。形成金属硅化物层可以包括暴露导电插塞的表面，在导电插头的暴露表面上沉积底部电极的金属层，并热处理半导体器件以使沉积的金属层和导电插塞的一部分反应以形成金属硅化物层。还提供了形成包括具有连接电容器的底部电极的金属硅化物层的电容器和导电插塞的半导体器件的方法。

5. 发明申请

US20050020066A1 Methods of forming a semiconductor device including a metal silicide layer between a conductive plug and a bottom electrode of a capacitor 有权
标题翻译：在电容器的导电插塞和底部电极之间形成包括金属硅化物层的半导体器件的方法
公开(公告)号：US20050020066A1
公开(公告)日：2005-01-27
申请号：US10863828
申请日：2004-06-08
申请人： Jeong-Sik Choi , Jung-Hee Chung , Woo-Gwan Shim , Young-Sun Kim , Jae-Hyoung Choi , Se-Hoon Oh , Cha-Young Yoo
发明人： Jeong-Sik Choi , Jung-Hee Chung , Woo-Gwan Shim , Young-Sun Kim , Jae-Hyoung Choi , Se-Hoon Oh , Cha-Young Yoo
IPC分类号： H01L27/108 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L21/20
CPC分类号： H01L28/91 , H01L21/76877 , H01L27/10855 , H01L27/11507 , H01L28/75
摘要： Embodiments of the present invention include methods of forming a contact to a capacitor in a semiconductor device. A metal silicide layer is formed at a top surface of a conductive plug of the semiconductor device that is coupled to a bottom electrode of the capacitor to provide an ohmic contact therebetween. Forming a metal silicide layer may include exposing a surface of the conductive plug, depositing a metal layer of the bottom electrode on the exposed surface of the conductive plug and thermally processing the semiconductor device to react a part of the deposited metal layer and the conductive plug to form the metal silicide layer. Methods of forming a semiconductor device including a capacitor having a metal silicide layer connecting a bottom electrode of the capacitor and a conductive plug are also provided.
摘要翻译：本发明的实施例包括在半导体器件中形成与电容器的接触的方法。金属硅化物层形成在半导体器件的导电插塞的顶表面上，该顶表面耦合到电容器的底部电极以在其间提供欧姆接触。形成金属硅化物层可以包括暴露导电插塞的表面，在导电插头的暴露表面上沉积底部电极的金属层，并热处理半导体器件以使沉积的金属层和导电插塞的一部分反应以形成金属硅化物层。还提供了形成包括具有连接电容器的底部电极的金属硅化物层的电容器和导电插塞的半导体器件的方法。

6. 发明申请

US20060046378A1 Methods of fabricating MIM capacitor employing metal nitride layer as lower electrode 审中-公开
标题翻译：使用金属氮化物层作为下电极制造MIM电容器的方法
公开(公告)号：US20060046378A1
公开(公告)日：2006-03-02
申请号：US11209541
申请日：2005-08-23
申请人： Jae-Hyoung Choi , Young-Sun Kim , Cha-Young Yoo , Jung-Hee Chung
发明人： Jae-Hyoung Choi , Young-Sun Kim , Cha-Young Yoo , Jung-Hee Chung
IPC分类号： H01L21/8244
CPC分类号： H01L21/76889 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L28/60
摘要： There are provided methods of fabricating a metal-insulator-metal (MIM) capacitor employing a metal nitride layer as a lower electrode. The method includes forming an insulating layer on a semiconductor substrate. A metal source gas and a nitride gas are supplied to the insulating layer, thereby depositing a metal nitride. A flushing gas including nitrogen is supplied to the metal nitride to enhance nitridation reaction. Along with the supply of a metal source gas and a nitride gas, the operation of supplying a flushing gas is performed at least one time alternately and repeatedly, thereby forming a metal nitride layer.
摘要翻译：提供了使用金属氮化物层作为下电极制造金属 - 绝缘体 - 金属（MIM）电容器的方法。该方法包括在半导体衬底上形成绝缘层。将金属源气体和氮化物气体供给到绝缘层，由此沉积金属氮化物。将包含氮气的冲洗气体供给到金属氮化物以增强氮化反应。随着供应金属源气体和氮化物气体，交替地和重复地进行至少一次的冲洗气体的供给操作，从而形成金属氮化物层。

7. 发明申请

US20090130457A1 DIELECTRIC STRUCTURE 审中-公开
标题翻译：电介质结构
公开(公告)号：US20090130457A1
公开(公告)日：2009-05-21
申请号：US12273360
申请日：2008-11-18
申请人： Wan-Don Kim , Jae-Hyoung Choi , Kyu-Ho Cho , Jung-Hee Chung , Jin-Yong Kim , Yong-Suk Tak
发明人： Wan-Don Kim , Jae-Hyoung Choi , Kyu-Ho Cho , Jung-Hee Chung , Jin-Yong Kim , Yong-Suk Tak
IPC分类号： B32B17/06
CPC分类号： H01G4/33 , H01G4/1218 , H01G4/20 , H01L28/56 , H01L28/91
摘要： A dielectric structure includes a first dielectric layer, a buffer oxide layer and a second dielectric layer. The lower dielectric layer has a material having a perovskite structure including titanium and is formed on a substrate. The buffer oxide layer is formed on the first dielectric layer. The second dielectric layer has a perovskite structure including titanium and is formed on the buffer oxide layer.
摘要翻译：电介质结构包括第一电介质层，缓冲氧化物层和第二电介质层。下介电层具有包含钛的钙钛矿结构并形成在基板上的材料。缓冲氧化物层形成在第一电介质层上。第二电介质层具有包含钛的钙钛矿结构，形成在缓冲氧化物层上。

8. 发明申请

US20070066015A1 Capacitor, method of forming the same, semiconductor device having the capacitor and method of manufacturing the same 有权
标题翻译：电容器，其形成方法，具有电容器的半导体器件及其制造方法
公开(公告)号：US20070066015A1
公开(公告)日：2007-03-22
申请号：US11523514
申请日：2006-09-20
申请人： Hong-Bum Park , Woo-Sung Lee , Nam-Kyu Kim , Jung-Hee Chung , Jae-Hyoung Choi
发明人： Hong-Bum Park , Woo-Sung Lee , Nam-Kyu Kim , Jung-Hee Chung , Jae-Hyoung Choi
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities. The upper electrode structure may be formed without generating voids between the dielectric layer and the upper electrode structure. The capacitor and the semiconductor device having the upper electrode structure may have improved electrical characteristics.
摘要翻译：示例性实施例涉及电容器，其形成方法，具有电容器的半导体器件及其制造方法。其他示例性实施例涉及具有包括第一上电极和第二上电极的上电极结构的电容器，其形成方法，具有电容器的半导体器件及其制造方法。在形成电容器的方法中，可以在基板上形成下电极，然后在下电极上形成电介质层。上电极结构可以形成在电介质层上。上电极结构可以包括第一上电极和第二上电极。第二上电极可以包括硅层，第一硅锗层和掺杂有p型杂质的第二硅锗层中的至少两个。可以形成上电极结构，而不会在电介质层和上电极结构之间产生空隙。具有上电极结构的电容器和半导体器件可具有改善的电特性。

9. 发明授权

US07482242B2 Capacitor, method of forming the same, semiconductor device having the capacitor and method of manufacturing the same 有权
标题翻译：电容器，其形成方法，具有电容器的半导体器件及其制造方法
公开(公告)号：US07482242B2
公开(公告)日：2009-01-27
申请号：US11523514
申请日：2006-09-20
申请人： Hong-Bum Park , Woo-Sung Lee , Nam-Kyu Kim , Jung-Hee Chung , Jae-Hyoung Choi
发明人： Hong-Bum Park , Woo-Sung Lee , Nam-Kyu Kim , Jung-Hee Chung , Jae-Hyoung Choi
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities. The upper electrode structure may be formed without generating voids between the dielectric layer and the upper electrode structure. The capacitor and the semiconductor device having the upper electrode structure may have improved electrical characteristics.
摘要翻译：示例性实施例涉及电容器，其形成方法，具有电容器的半导体器件及其制造方法。其他示例性实施例涉及具有包括第一上电极和第二上电极的上电极结构的电容器，其形成方法，具有电容器的半导体器件及其制造方法。在形成电容器的方法中，可以在基板上形成下电极，然后在下电极上形成电介质层。上电极结构可以形成在电介质层上。上电极结构可以包括第一上电极和第二上电极。第二上电极可以包括硅层，第一硅锗层和掺杂有p型杂质的第二硅锗层中的至少两个。可以形成上电极结构，而不会在电介质层和上电极结构之间产生空隙。具有上电极结构的电容器和半导体器件可具有改善的电特性。

10. 发明申请

US20060099760A1 Storage capacitors for semiconductor devices and methods of forming the same 有权
标题翻译：用于半导体器件的存储电容器及其形成方法
公开(公告)号：US20060099760A1
公开(公告)日：2006-05-11
申请号：US11266520
申请日：2005-11-03
申请人： Rak-Hwan Kim , Young-Joo Cho , Sung-Tae Kim , In-Sun Park , Hyeon-Deok Lee , Hyun-Suk Lee , Jung-Hee Chung , Hyun-Young Kim , Hyun-Seok Lim
发明人： Rak-Hwan Kim , Young-Joo Cho , Sung-Tae Kim , In-Sun Park , Hyeon-Deok Lee , Hyun-Suk Lee , Jung-Hee Chung , Hyun-Young Kim , Hyun-Seok Lim
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/75
摘要： Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.
摘要翻译：形成存储电容器的方法包括在半导体衬底上形成具有开口的层间绝缘层，在开口中形成接触插塞，在层间绝缘层和接触插塞上形成模压氧化层，选择性地去除模制件的部分在接触塞上方形成凹部，在凹部的底面和侧面形成钛层，在钛层上形成氮化钛层，在氮化钛层上形成氮化钛层。存储电容器包括半导体衬底，在衬底上具有接触插塞的层间绝缘层，以及包括钛硅化物层的接触插塞上的存储电极，硅化钛层上的氮化钛层和氧化钛氮化物层在氮化钛层上。

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