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1. 发明授权

US08291417B2 Trace buffer with a processor 有权
标题翻译：具有处理器的跟踪缓冲区
公开(公告)号：US08291417B2
公开(公告)日：2012-10-16
申请号：US11530051
申请日：2006-09-08
申请人： Kun Xu , Jen-Tien Yen
发明人： Kun Xu , Jen-Tien Yen
IPC分类号： G06F9/46 , G06F11/00 , G06F3/00
CPC分类号： G06F11/3476 , G06F11/3466 , G06F2201/87
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译：一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。

2. 发明授权

US07813908B2 Clock control module simulator and method thereof 有权
标题翻译：时钟控制模块及其方法
公开(公告)号：US07813908B2
公开(公告)日：2010-10-12
申请号：US11741251
申请日：2007-04-27
申请人： Jen-Tien Yen , Jeff B. Golden , Richard G. Woltenberg
发明人： Jen-Tien Yen , Jeff B. Golden , Richard G. Woltenberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock control model. Accordingly, the simulated power state of the portion of the integrated circuit model to be clocked by a clock control model can be monitored based on the indicator from the clock control model, rather than on a higher level analysis of the simulated input/output behavior of the integrated circuit model.
摘要翻译：一种用于模拟具有多个时钟控制模块的集成电路的方法包括模拟集成电路，并且在仿真期间从每个时钟控制模型自动接收时钟控制模型的模拟功率状态的指示。因此，可以基于来自时钟控制模型的指示符来监视由时钟控制模型计时的集成电路模型的部分的模拟功率状态，而不是基于对模拟输入/输出行为的更高级别分析集成电路模型。

3. 发明申请

US20080270099A1 CLOCK CONTROL MODULE SIMULATOR AND METHOD THEREOF 有权
标题翻译：时钟控制模块及其方法
公开(公告)号：US20080270099A1
公开(公告)日：2008-10-30
申请号：US11741251
申请日：2007-04-27
申请人： Jen-Tien Yen , Jeff B. Golden , Richard G. Woltenberg
发明人： Jen-Tien Yen , Jeff B. Golden , Richard G. Woltenberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock control model. Accordingly, the simulated power state of the portion of the integrated circuit model to be clocked by a clock control model can be monitored based on the indicator from the clock control model, rather than on a higher level analysis of the simulated input/output behavior of the integrated circuit model.
摘要翻译：一种用于模拟具有多个时钟控制模块的集成电路的方法包括模拟集成电路，并且在仿真期间从每个时钟控制模型自动接收时钟控制模型的模拟功率状态的指示。因此，可以基于来自时钟控制模型的指示符来监视由时钟控制模型计时的集成电路模型的部分的模拟功率状态，而不是基于对模拟输入/输出行为的更高级别分析集成电路模型。

4. 发明授权

US06567934B1 Method and apparatus for verifying multiprocessing design in a unit simulation environment 失效
标题翻译：用于在单元仿真环境中验证多处理设计的方法和装置
公开(公告)号：US06567934B1
公开(公告)日：2003-05-20
申请号：US09422312
申请日：1999-10-21
申请人： Jen-Tien Yen , Qichao Richard Yin
发明人： Jen-Tien Yen , Qichao Richard Yin
IPC分类号： G06F1100
CPC分类号： G06F17/5022
摘要： A method and apparatus for verification of designed logic in a processing unit (100) that performs multiprocessing functions is presented. Once the multiprocessing unit to be exercised as the device under test (350) is defined, an irritator (330) is constructed to provide the stimuli to the interface of the device under test (350) such that the device under test (350) is exercised. The irritator (330) receives instructions (314) as its input, where relevant instructions are converted to transactional stimulus that is applied to the device under test (350). The irritator (330) also monitors the interface of the device under test (350) to detect when multiprocessing operations executed by other processing units (340) included in the system (5) require a response. The response is produced via signal stimulus on the interface of the device under test (350) to which the irritator (330) is coupled.
摘要翻译：提出了一种在执行多处理功能的处理单元（100）中验证设计逻辑的方法和装置。一旦定义要作为被测设备（350）行使的多处理单元，则构造刺激器（330）以将被刺激装置（350）提供给被测设备（350）的接口，使得被测设备（350）为行使。刺激器（330）接收指令（314）作为其输入，其中相关指令被转换为施加到被测设备（350）的事务性刺激。刺激器（330）还监视被测设备（350）的接口以检测由系统（5）中包括的其他处理单元（340）执行的多处理操作何时需要响应。响应是通过激发器（330）耦合到的被测设备（350）的接口上的信号刺激产生的。

5. 发明授权

US06505149B1 Method and system for verifying a source-synchronous communication interface of a device 失效
标题翻译：用于验证设备的源同步通信接口的方法和系统
公开(公告)号：US06505149B1
公开(公告)日：2003-01-07
申请号：US09365387
申请日：1999-08-02
申请人： Mark Griswold , Jen-Tien Yen
发明人： Mark Griswold , Jen-Tien Yen
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , H04L7/0008
摘要： A method for verifying a source-synchronous communication interface of a processor is disclosed. A software model of a first device having a source-synchronous communication interface and a software model of a second device capable of communicating with the first device via the source-synchronous communication interface are provided. The source-synchronous communication interface includes an applied clock line, an address line, an echo clock line, and a data line. A simulation of a data request from the first device model to the second device model via an applied clock signal along with an address on the applied clock line and the address line is initially performed. The requested data is then received by the first device model from the second device model via the data line after various delays between the applied clock signal and an echo clock signal on the applied clock line and the echo clock line, respectively. Finally, the requested data received by the first device model is verified as to its veracity.
摘要翻译：公开了一种用于验证处理器的源同步通信接口的方法。提供具有源同步通信接口和能够经由源同步通信接口与第一设备进行通信的第二设备的软件模型的第一设备的软件模型。源同步通信接口包括应用的时钟线，地址线，回波时钟线和数据线。最初执行通过施加的时钟信号以及所施加的时钟线和地址线上的地址从第一设备模型到第二设备模型的数据请求的模拟。然后，在所施加的时钟信号和所应用的时钟线和回波时钟线上的回波时钟信号之间的各种延迟之后，所请求的数据然后经由数据线从第二设备模型接收第一设备模型。最后，验证第一设备模型接收到的请求数据的真实性。

6. 发明授权

US08645117B2 Clock simulation device and methods thereof 有权
标题翻译：时钟仿真装置及其方法
公开(公告)号：US08645117B2
公开(公告)日：2014-02-04
申请号：US12788769
申请日：2010-05-27
申请人： Qichao R. Yin , Jen-Tien Yen , Wai Chee Wong
发明人： Qichao R. Yin , Jen-Tien Yen , Wai Chee Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A pulse width of a simulated external system clock is set by determining a least common multiple of the frequency of selected internal clock signals relative to the frequency of the external system clock. The pulse width can be further adjusted based on the frequency of simulated external clocks. By setting the pulse width of the simulated external system clock based on the least common multiple value, the time required to complete the simulation can be reduced while ensuring proper operation of the simulated clock signals during the simulation.
摘要翻译：通过相对于外部系统时钟的频率确定所选择的内部时钟信号的频率的最小公倍数来设置模拟外部系统时钟的脉冲宽度。可以根据模拟外部时钟的频率进一步调整脉冲宽度。通过基于最小公倍数设置模拟外部系统时钟的脉冲宽度，可以在模拟期间确保模拟时钟信号的正确运行，从而可以减少完成仿真所需的时间。

7. 发明申请

US20110295586A1 CLOCK SIMULATION DEVICE AND METHODS THEREOF 有权
标题翻译：时钟模拟装置及其方法
公开(公告)号：US20110295586A1
公开(公告)日：2011-12-01
申请号：US12788769
申请日：2010-05-27
申请人： Qichao R. Yin , Wai Chee Wong , Jen-Tien Yen
发明人： Qichao R. Yin , Wai Chee Wong , Jen-Tien Yen
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A pulse width of a simulated external system clock is set by determining a least common multiple of the frequency of selected internal clock signals relative to the frequency of the external system clock. The pulse width can be further adjusted based on the frequency of simulated external clocks. By setting the pulse width of the simulated external system clock based on the least common multiple value, the time required to complete the simulation can be reduced while ensuring proper operation of the simulated clock signals during the simulation.
摘要翻译：通过相对于外部系统时钟的频率确定所选择的内部时钟信号的频率的最小公倍数来设置模拟外部系统时钟的脉冲宽度。可以根据模拟外部时钟的频率进一步调整脉冲宽度。通过基于最小公倍数设置模拟外部系统时钟的脉冲宽度，可以在模拟期间确保模拟时钟信号的正确运行，从而可以减少完成仿真所需的时间。

8. 发明授权

US06542861B1 Simulation environment cache model apparatus and method therefor 失效
标题翻译：模拟环境缓存模型的设备及方法
公开(公告)号：US06542861B1
公开(公告)日：2003-04-01
申请号：US09282618
申请日：1999-03-31
申请人： Joseph William Lyles, Jr. , Jen-Tien Yen
发明人： Joseph William Lyles, Jr. , Jen-Tien Yen
IPC分类号： G06F944
CPC分类号： G06F12/0897 , G06F2212/1032
摘要： A cache model apparatus and method are implemented. A set of predetermined protocols for generating cache block movement events driving level one (L1) cache to level two (L2) cache traffic in a simulation environment are provided. An event protocol is selected for a test case in response to user input, or alternatively, a random selection is made. In accordance with the protocol selected, castouts of modified L1 cache lines are generated.
摘要翻译：实现了缓存模型装置和方法。提供了一组用于在模拟环境中产生将一级（L1）高速缓存驱动到二级（L2）高速缓存流量的高速缓存块移动事件的预定协议。响应于用户输入为测试用例选择事件协议，或者替代地进行随机选择。根据所选择的协议，生成修改的L1高速缓存行的转换。

9. 发明申请

US20100313092A1 TECHNIQUE FOR INITIALIZING DATA AND INSTRUCTIONS FOR CORE FUNCTIONAL PATTERN GENERATION IN MULTI-CORE PROCESSOR 有权
标题翻译：用于初始化多核处理器中核心功能模式的数据和指令的技术
公开(公告)号：US20100313092A1
公开(公告)日：2010-12-09
申请号：US12479535
申请日：2009-06-05
申请人： Kun Xu , Jen-Tien Yen , Robert Serphillips
发明人： Kun Xu , Jen-Tien Yen , Robert Serphillips
IPC分类号： G01R31/28
CPC分类号： G06F11/2236
摘要： Techniques have been developed to introduce processor core functional pattern tests into a memory space addressable by at least one processor core of an integrated circuit. In general, such functional pattern tests can include both instruction sequences and data patterns and, in some embodiments in accordance with the present invention, are introduced (at least in part) into on-chip cache memory using facilities of an on-chip loader. Instruction opcodes used in functional test sequences may be efficiently introduced into a plurality of target locations in memory (e.g., at locations corresponding to multiple interrupt handlers or at locations from which a multiplicity of cores execute their functional tests) using facilities of the on-chip loader. In some embodiments, instruction selections together with a base address, extent and stride indications may be used to direct operation of the on-chip loader. Likewise, data patterns used in the functional test sequences may be specified as a data pattern selection together with base address, extent and optional stride indications and introduced into a plurality of target memory locations using facilities of the on-chip loader. In some embodiments, other forms or encodings of directives may be used.
摘要翻译：已经开发了将处理器核心功能模式测试引入由集成电路的至少一个处理器核可寻址的存储器空间的技术。通常，这样的功能模式测试可以包括指令序列和数据模式，并且在根据本发明的一些实施例中，使用片上加载器的设备将（至少部分地）引入到片上高速缓冲存储器中。在功能测试序列中使用的指令操作码可以有效地引入存储器中的多个目标位置（例如，在与多个中断处理程序相对应的位置处，或者使用多个核心执行其功能测试的位置）装载机在一些实施例中，可以使用指令选择以及基地址，范围和步幅指示来引导片上加载器的操作。类似地，在功能测试序列中使用的数据模式可以被指定为与基地址，范围和可选步幅指示一起的数据模式选择，并且使用片上加载器的设施被引入到多个目标存储器位置。在一些实施例中，可以使用指令的其他形式或编码。

10. 发明申请

US20080127187A1 TRACE BUFFER WITH A PROCESSOR 有权
标题翻译：跟加工商的缓冲区
公开(公告)号：US20080127187A1
公开(公告)日：2008-05-29
申请号：US11530051
申请日：2006-09-08
申请人： Kun Xu , Jen-Tien Yen
发明人： Kun Xu , Jen-Tien Yen
IPC分类号： G06F9/46
CPC分类号： G06F11/3476 , G06F11/3466 , G06F2201/87
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译：一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。

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