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1. 发明申请

US20090327986A1 GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS 有权
标题翻译：对具有定时异常电位的电子电路刺激模式的响应
公开(公告)号：US20090327986A1
公开(公告)日：2009-12-31
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

2. 发明授权

US08527232B2 Diagnostic test pattern generation for small delay defect 有权
标题翻译：诊断测试模式生成小延迟缺陷
公开(公告)号：US08527232B2
公开(公告)日：2013-09-03
申请号：US12768592
申请日：2010-04-27
申请人： Ruifeng Guo , Wu-Tung Cheng , Takeo Kobayashi , Kun-Han Tsai
发明人： Ruifeng Guo , Wu-Tung Cheng , Takeo Kobayashi , Kun-Han Tsai
IPC分类号： G01R31/00
CPC分类号： G01R31/318328
摘要： Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.
摘要翻译：小延迟缺陷的诊断测试模式生成方法基于识别和激活穿过诊断嫌疑人的长途径。根据某些标准确定长路径，例如使用SDF（标准延迟格式）定时信息计算的路径延迟值和路径上的逻辑门数。在本发明的一些实施例中，长路径是穿过诊断嫌疑人并且到达从故障日志中选择的相应故障观察点的最长路径，并且为每个这样的对识别N个最长路径。

3. 发明授权

US08468409B2 Speed-path debug using at-speed scan test patterns 有权
标题翻译：使用速度扫描测试模式的速度路径调试
公开(公告)号：US08468409B2
公开(公告)日：2013-06-18
申请号：US12634682
申请日：2009-12-09
申请人： Ruifeng Guo , Wu-Tung Cheng , Kun-Han Tsai
发明人： Ruifeng Guo , Wu-Tung Cheng , Kun-Han Tsai
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318577
摘要： Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked.
摘要翻译：基于速度扫描测试模式的速度路径调试技术。基于检测到的高速扫描模式故障和未知的X值模拟识别潜在速度路径。当识别的速度路径数量大时，可疑速度路径被排序。

4. 发明申请

US20100185908A1 Speed-Path Debug Using At-Speed Scan Test Patterns 有权
标题翻译：使用速度扫描测试模式的速度路径调试
公开(公告)号：US20100185908A1
公开(公告)日：2010-07-22
申请号：US12634682
申请日：2009-12-09
申请人： Ruifeng Guo , Wu-Tung Cheng , Kun-Han Tsai
发明人： Ruifeng Guo , Wu-Tung Cheng , Kun-Han Tsai
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318594 , G01R31/318577
摘要： Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked.
摘要翻译：基于速度扫描测试模式的速度路径调试技术。基于检测到的高速扫描模式故障和未知的X值模拟识别潜在速度路径。当识别的速度路径数量大时，可疑速度路径被排序。

5. 发明申请

US20070283202A1 COMPACTOR INDEPENDENT FAULT DIAGNOSIS 有权
标题翻译：压力计独立故障诊断
公开(公告)号：US20070283202A1
公开(公告)日：2007-12-06
申请号：US11772648
申请日：2007-07-02
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

6. 发明申请

US20050222816A1 Compactor independent fault diagnosis 有权
标题翻译：压实机独立故障诊断
公开(公告)号：US20050222816A1
公开(公告)日：2005-10-06
申请号：US10925230
申请日：2004-08-23
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

7. 发明授权

US10509073B2 Timing-aware test generation and fault simulation 有权
公开(公告)号：US10509073B2
公开(公告)日：2019-12-17
申请号：US15664169
申请日：2017-07-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/3183 , G01R31/3177 , G06F17/50
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

8. 发明授权

US08560906B2 Timing-aware test generation and fault simulation 有权
公开(公告)号：US08560906B2
公开(公告)日：2013-10-15
申请号：US13285899
申请日：2011-10-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

9. 发明申请

US20120174049A1 TIMING-AWARE TEST GENERATION AND FAULT SIMULATION 有权
标题翻译：定时测试生成和故障模拟
公开(公告)号：US20120174049A1
公开(公告)日：2012-07-05
申请号：US13285899
申请日：2011-10-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

10. 发明授权

US07984354B2 Generating responses to patterns stimulating an electronic circuit with timing exception paths 有权
标题翻译：产生对具有定时异常路径刺激电子电路的模式的响应
公开(公告)号：US07984354B2
公开(公告)日：2011-07-19
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

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